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G. N. Nandakumar
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2010 – 2019
- 2011
- [i1]Santanu Bhowmick, Sanjay Bhattacherjee, G. N. Nandakumar:
Generation of Test Vectors for Sequential Cell Verification. CoRR abs/1110.6105 (2011)
2000 – 2009
- 2005
- [c5]G. N. Nandakumar, Nirav Patel, Raghunatha Reddy, Makeshwar Kothandaraman:
Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models. VLSI Design 2005: 757-761 - 2004
- [c4]Nirav Patel, M. Srihari, Pooja Maheswari, G. N. Nandakumar:
An Efficient Method to Generate Test Vectors for Combinational Cell Verification. VLSI Design 2004: 769-772
1990 – 1999
- 1998
- [c3]Abhijit Das, Samrat Sen, Mohan Rangan, Rupesh Nayak, G. N. Nandakumar:
False Path Detection at Transistor Level. VLSI Design 1998: 226-229 - 1993
- [c2]Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa:
Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. ITC 1993: 139-148 - [c1]Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin:
Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. VLSI Design 1993: 140-143
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