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Jong-Moon Choi
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2020 – today
- 2021
- [j2]Jong-Moon Choi
, Do-Wan Kwon, Je-Joong Woo, Eun-Je Park, Kee-Won Kwon
:
Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2863-2875 (2021) - 2020
- [c6]Eun-Je Park, Jong-Moon Choi, Do-Wan Kwon, Je-Joong Woo, Kee-Won Kwon:
A 35x10 Charge-Trap Synaptic Memory for 57xMatrix Recognition. AICAS 2020: 99-102 - [c5]Segi Lee, Sugil Lee, Jongeun Lee, Jong-Moon Choi, Do-Wan Kwon, Seung-Kwang Hong, Kee-Won Kwon:
Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor. ACM Great Lakes Symposium on VLSI 2020: 427-432 - [c4]Sang-Won Kim, Jae-Hyuk Yang, Eun-Je Park, Jong-Moon Choi, Kee-Won Kwon:
A High Efficiency Variable Stage and Frequency Charge Pump for Wide Range ISPP. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c3]Yong-Hyun Kim, Jong-Moon Choi, Je-Joong Woo, Eun-Je Park, Sang-Won Kim, Kee-Won Kwon:
A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device. ICEIC 2019: 1-4 - [c2]Je-Joong Woo, Jong-Moon Choi, Kee-Won Kwon:
CMOS-Compatible Learning Device for Neuromorphic Synapse Application using Adjustable Hot Carrier Injections. MWSCAS 2019: 57-60 - 2017
- [j1]Soon-Chan Kwon
, Jong-Min Baek, Jong-Moon Choi, Kee-Won Kwon:
A Fast and Reliable Cross-Point Three-State/Cell ReRAM. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1622-1631 (2017) - 2016
- [c1]Sangheon Lee, Jeonghwan Song, Changhyuk Seong, Jiyong Woo, Jong-Moon Choi, Soon-Chan Kwon, Ho-Joon Kim, Hyun-Suk Kang, Soo Gil Kim, Hoe Gwon Jung, Kee-Won Kwon, Hyunsang Hwang:
Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier. VLSI Circuits 2016: 1-2
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