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2020 – today
- 2024
[c8]Jaehyeok Yang, Hyeongjun Ko, Kyunghoon Kim, Hyunsu Park, Jihwan Park, Ji-Hyo Kang, Jin-Youp Cha, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Boram Kim, Sang-Yeon Byeon, Sungkwon Lee, Hyeonyeol Park, Joohwan Cho, Jonghwan Kim:
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry. ISSCC 2024: 232-234
2010 – 2019
- 2019
- [c7]Gyunam Jeon, Kyung Ki Kim, Yong-Bin Kim:
Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation. ISOCC 2019: 241-242 - [c6]Gyunam Jeon, Yong-Bin Kim:
10 GHz Standing Wave Oscillator Based Clock Distribution Network Considering Distributed Capacitance. MWSCAS 2019: 694-697 - 2018
- [j1]Yongsuk Choi, Gyunam Jeon, Yong-Bin Kim:
Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme. Integr. 63: 148-159 (2018) - [c5]Gyunam Jeon, Yong-Bin Kim:
Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor. MWSCAS 2018: 1-4 - 2017
- [c4]Gyunam Jeon, Yong-Bin Kim:
Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate. ACM Great Lakes Symposium on VLSI 2017: 439-442 - [c3]Gyunam Jeon, Yong-Bin Kim:
A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction. ISCAS 2017: 1-4 - [c2]Gyunam Jeon, Yong-Bin Kim:
A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap. ISOCC 2017: 244-245 - 2016
- [c1]Chen Zhang, Gyunam Jeon, Yongsuk Choi, Yong-Bin Kim, Kyung Ki Kim:
An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction. NATW 2016: 6-11
Coauthor Index
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