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Yu-Hao Ho

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Conference and Workshop Papers

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2018
[c3]
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  - conf/vlsi-dat/ChenHCYLL18
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  - https://dblp.org/rec/conf/vlsi-dat/ChenHCYLL18
Yu-Wei Chen, Yu-Hao Ho, Chih-Ming Chang, Kai-Chieh Yang, Ming-Ting Li, James Chien-Mo Li:
Parallel order ATPG for test compaction. VLSI-DAT 2018: 1-4
2017
[c2]
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  - conf/vlsi-dat/HoCCYL17
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Yu-Hao Ho, Yo-Wei Chen, Chih-Ming Chang, Kai-Chieh Yang, James Chien-Mo Li:
Robust test pattern generation for hold-time faults in nanometer technologies. VLSI-DAT 2017: 1-4
2015
[c1]
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  - conf/ats/ChiangHCPL15
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Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, James Chien-Mo Li:
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. ATS 2015: 181-186

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