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Tobias Lieske
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2010 – 2019
- 2019
- [j2]Marc Reichenbach
, Philipp Holzinger
, Konrad Häublein
, Tobias Lieske, Paul Blinzer, Dietmar Fey:
Heterogeneous Computing Utilizing FPGAs - A New and Flexible Approach Integrating Dedicated Hardware Accelerators into Common Computing Platforms. J. Signal Process. Syst. 91(7): 745-757 (2019) - [j1]Tobias Lieske
, Wilfried Uhring
, Norbert Dumas, Anastasia Ioanna Skilitski, Jérémie Léonard, Dietmar Fey:
Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications. J. Signal Process. Syst. 91(7): 819-831 (2019) - 2018
- [c8]Tobias Lieske, Mehrdad Biglari, Dietmar Fey:
Multi-level memristive voltage divider: programming scheme trade-offs. MEMSYS 2018: 259-268 - [c7]Mehrdad Biglari, Tobias Lieske, Dietmar Fey:
High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States. NANOARCH 2018: 19-24 - [c6]Johannes Knödtel, Wolffhardt Schwabe, Tobias Lieske, Marc Reichenbach
, Dietmar Fey:
A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs. PATMOS 2018: 46-53 - 2017
- [c5]Tobias Lieske, Wilfried Uhring
, Norbert Dumas, Jérémie Léonard, Dietmar Fey:
Embedded fluorescence lifetime determination for high throughput real-time droplet sorting with microfluidics. DASIP 2017: 1-6 - [c4]Marc Reichenbach
, Philipp Holzinger
, Konrad Häublein, Tobias Lieske, Paul Blinzer, Dietmar Fey:
LibHSA: One step towards mastering the era of heterogeneous hardware accelerators using FPGAs. DASIP 2017: 1-6 - [c3]Tobias Lieske, Benjamin Pfundt, Steffen Vaas, Marc Reichenbach
, Dietmar Fey:
System on chip generation for multi-sensor and sensor fusion applications. SAMOS 2017: 20-29 - 2016
- [c2]Tobias Lieske, Marc Reichenbach
, Burkhard Ringlein
, Dietmar Fey:
Dataflow optimization for programmable embedded image preprocessing accelerators. ReConFig 2016: 1-8 - 2015
- [c1]Marc Reichenbach
, Tobias Lieske, Steffen Vaas, Konrad Häublein, Dietmar Fey:
FAUPU - A design framework for the development of programmable image processing architectures. ReConFig 2015: 1-8
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