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Asisa Kumar Panigrahi
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2020 – today
- 2022
- [c7]Srinivas Varma, Ch Pratyusha Chowdari, D. Jayanthi, Asisa Kumar Panigrahi, K. Jamal:
TCAD Simulation of a 10nm n-Channel Vertical Double Gate Silicon On Insulator MOSFET for Digital Applications. ICCCNT 2022: 1-6
2010 – 2019
- 2016
- [c6]Kumail Khurram, Asisa Kumar Panigrahi
, Satish Bonam
, Om Krishan Singh, Shiv Govind Singh:
Novel inter layer dielectric and thermal TSV material for enhanced heat mitigation in 3-D IC. 3DIC 2016: 1-4 - [c5]C. Hemanth Kumar, Asisa Kumar Panigrahi
, Om Krishan Singh, Shiv Govind Singh:
Noise performance improvement through optimized stacked layer of liner structure around the TSV in 3D IC. 3DIC 2016: 1-4 - [c4]Asisa Kumar Panigrahi
, Satish Bonam
, Tamal Ghosh, Siva Rama Krishna Vanjari, Shiv Govind Singh:
Low temperature CMOS compatible Cu-Cu thermo-compression bonding with constantan alloy passivation for 3D IC integration. 3DIC 2016: 1-4 - [c3]Suraj Patil, Asisa Kumar Panigrahi
, Satish Bonam
, C. Hemanth Kumar, Om Krishan Singh, Shiv Govind Singh:
Improved noise coupling performance using optimized Teflon liner with different TSV structures for 3D IC integration. 3DIC 2016: 1-4 - [c2]Suraj Singh, Asisa Kumar Panigrahi
, Om Krishan Singh, Shiv Govind Singh:
Analysis of graphene and CNT based finned TTSV and spreaders for thermal management in 3D IC. 3DIC 2016: 1-4 - 2015
- [c1]Asisa Kumar Panigrahi
, Satish Bonam
, Tamal Ghosh, Siva Rama Krishna Vanjari, Shiv Govind Singh:
Long term efficacy of ultra-thin Ti passivation layer for achieving low temperature, low pressure Cu-Cu Wafer-on-Wafer bonding. 3DIC 2015: TS8.13.1-TS8.13.5
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last updated on 2024-04-24 22:45 CEST by the dblp team
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