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ORCIDHuan-Neng Ron Chen
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2010 – 2019
- 2019
[j5]Yanghyo Kim
, Boyu Hu, Yuan Du, Wei-Han Cho, Rulin Huang, Adrian Tang, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang:
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications. IEEE J. Solid State Circuits 54(6): 1600-1612 (2019)- [j4]Kai Xu, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski:
A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation. IEEE J. Solid State Circuits 54(7): 2028-2037 (2019) - [c9]Feng-Wei Kuo, Zhirui Zong, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski:
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic. ESSCIRC 2019: 53-56 - 2018
- [j3]Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski:
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3756-3768 (2018) - [c8]Yanghyo Kim, Boyu Hu, Yuan Du, Adrian Tang, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang:
A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications. ISSCC 2018: 278-280 - 2017
- [j2]Feng-Wei Kuo, Sandro Binsfeld Ferreira, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Iman Madadi, Massoud Tohidian, Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski:
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network. IEEE J. Solid State Circuits 52(4): 1144-1162 (2017) - 2016
- [j1]Masoud Babaie, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Mina Shahmohammadi, Robert Bogdan Staszewski:
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm. IEEE J. Solid State Circuits 51(7): 1547-1565 (2016) - [c7]Yan Zhao, Zuow-Zun Chen, Gabriel Virbila, Yinuo Xu, Richard Al Hadi, Yanghyo Kim, Adrian Tang, Theodore Reck, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang:
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS. ISSCC 2016: 36-37 - [c6]Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang:
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. ISSCC 2016: 184-185 - [c5]Feng-Wei Kuo, Sandro Binsfeld Ferreira, Masoud Babaie, Huan-Neng Ron Chen, Lan-chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Guanzhong Huang, Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski:
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter. VLSI Circuits 2016: 1-2 - 2015
- [c4]Chuei-Tang Wang, Jeng-Shien Hsieh, Victor C. Y. Chang, En-Hsiang Yeh, Feng-Wei Kuo, Hsu-Hsien Chen, Chih-Hua Chen, Huan-Neng Ron Chen, Ying-Ta Lu, Chewnpu Jou, Hao-Yi Tsai, C. S. Liu, Doug C. H. Yu:
Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology. 3DIC 2015: TS6.3.1-TS6.3.4 - [c3]Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Kyle Yen, Jinn-Yeh Chien, Lanchou Cho, Fred Kuo, Chewnpu Jou, Fu-Lung Hsueh, Robert Bogdan Staszewski:
A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm. ESSCIRC 2015: 356-359 - [c2]Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan, Huan-Neng Ron Chen, Chewnpu Jou, Ming-Hsien Tsai, Fu-Lung Hsueh, Mau-Chung Frank Chang:
14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. ISSCC 2015: 1-3 - 2014
- [c1]Feng-Wei Kuo, Huan-Neng Ron Chen, Kyle Yen, Hsien-Yuan Liao, Chewnpu Jou, Fu-Lung Hsueh, Masoud Babaie, Robert Bogdan Staszewski:
A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS. VLSIC 2014: 1-2
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