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ORCIDDongil Lee
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Journal Articles
- 2020
[j9]Daewoong Lee
, Dongil Lee, Yong-Hun Kim, Hyun-Kyu Jeon, Byung-Guk Kim, Lee-Sup Kim:
A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 67-71 (2020)- 2019
- [j8]Chongsoo Jung, Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim:
A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1972-1976 (2019) - [j7]Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim:
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 724-728 (2019) - 2018
- [j6]Yong-Hun Kim, Dongil Lee, Daewoong Lee, Lee-Sup Kim:
A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1539-1543 (2018) - [j5]Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim:
A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1564-1568 (2018) - 2017
- [j4]Yong-Hun Kim, Taeho Lee, Hyun-Kyu Jeon, Dongil Lee, Lee-Sup Kim:
An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 823-835 (2017) - 2016
- [j3]Sungsoon Kim, Dongil Lee:
Standard monomials for temperley-lieb algebras. ACM Commun. Comput. Algebra 50(4): 179-181 (2016) - [j2]Dongil Lee, Taeho Lee, Young-Ju Kim, Lee-Sup Kim:
A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector. IEEE Trans. Circuits Syst. II Express Briefs 63-II(8): 733-737 (2016) - 2015
- [j1]Dongil Lee:
Standard monomials for the Weyl group F4. ACM Commun. Comput. Algebra 49(3): 74-76 (2015)
Conference and Workshop Papers
- 2024
- [c4]Kyeongtae Nam, Jaehyuk Kim, Dongil Lee, Kyuchang Kang, Sangyun Kim, ChangYoung Lee, Hyunchul Yoon, Donggeon Kim, Bokyeon Won, Jaejoon Song, Incheol Nam, Young-Hun Seo, Jeong-Don Ihm, Changsik Yoo, Sangjoon Hwang:
An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM. VLSI Technology and Circuits 2024: 1-2 - 2019
- [c3]Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim:
A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS. VLSI Circuits 2019: 196- - 2015
- [c2]Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, Lee-Sup Kim:
An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider. CICC 2015: 1-4 - [c1]Daewoong Lee, Dongil Lee, Taeho Lee, Yong-Hun Kim, Lee-Sup Kim:
An integrated time register and arithmetic circuit with combined operation for time-domain signal processing. ISCAS 2015: 1830-1833
Informal and Other Publications
- 2016
- [i1]Seymour Knowles-Barley, Verena Kaynig, Thouis Ray Jones, Alyssa Wilson, Joshua Morgan, Dongil Lee, Daniel R. Berger, Narayanan Kasthuri, Jeff W. Lichtman, Hanspeter Pfister:
RhoanaNet Pipeline: Dense Automatic Neural Annotation. CoRR abs/1611.06973 (2016)
Coauthor Index
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