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2020 – today
- 2021
[j1]David Bol
, Maxime Schramme, Ludovic Moreau, Pengcheng Xu, Rémi Dekimpe, Roghayeh Saeidi, Thomas Haine, Charlotte Frenkel, Denis Flandre:
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. IEEE J. Solid State Circuits 56(7): 2256-2269 (2021)
2010 – 2019
- 2019
- [c5]David Bol, Maxime Schramme, Ludovic Moreau, Thomas Haine, Pengcheng Xu, Charlotte Frenkel, Remi Dekimpe, François Stas, Denis Flandre:
A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. ISSCC 2019: 322-324 - 2018
- [c4]Thomas Haine, Johan Segers, Denis Flandre, David Bol:
Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics. DATE 2018: 195-200 - 2017
- [c3]Thomas Haine, Quoc-Khoi Nguyen, François Stas, Ludovic Moreau, Denis Flandre, David Bol:
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. ESSCIRC 2017: 312-315 - 2016
- [c2]Thomas Haine, François Stas, Guerric de Streel, Cecilia Gimeno, Denis Flandre, David Bol:
CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array. ICDSC 2016: 155-159 - 2015
- [c1]Ahmed T. Elthakeb, Thomas Haine, Denis Flandre, Yehea Ismail, Hamdy Abd Elhamid, David Bol:
Analysis and optimization for dynamic read stability in 28nm SRAM bitcells. ISCAS 2015: 1414-1417
Coauthor Index
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