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2020 – today
- 2024
[c15]Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich:
ALPACA: An Accelerator Chip for Nested Loop Programs. ISCAS 2024: 1-5- 2021
- [b1]Michael Witterauf:
A Compiler for Symbolic Code Generation for Tightly Coupled Processor Arrays. University of Erlangen-Nuremberg, Germany, 2021 - [j6]Marcel Brand
, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33(14) (2021) - [j5]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. 20(5): 49:1-49:31 (2021) - [c14]Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jürgen Teich:
Aarith: an arbitrary precision number library. SAC 2021: 529-534 - [i1]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR abs/2101.04395 (2021) - 2020
- [c13]Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich:
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. ASAP 2020: 157-164 - [c12]Dominik Walter, Michael Witterauf, Jürgen Teich:
Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. MEMOCODE 2020: 1-11
2010 – 2019
- 2019
- [j4]Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich:
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. J. Comput. 14(8): 541-556 (2019) - [c11]Marcel Brand, Michael Witterauf, Frank Hannig, Jürgen Teich:
Anytime instructions for programmable accuracy floating-point arithmetic. CF 2019: 215-219 - [c10]Michael Witterauf, Frank Hannig, Jürgen Teich:
Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. MEMOCODE 2019: 8:1-8:10 - 2018
- [j3]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. 17(2): 31:1-31:27 (2018) - [c9]Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP 2018: 1-9 - [c8]Michael Witterauf, Jürgen Teich:
Run-time Requirement Enforcement for Loop Programs on Processor Arrays. MEMOCODE 2018: 22-32 - 2017
- [c7]Michael Witterauf, Frank Hannig, Jürgen Teich:
Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. RSP 2017: 9-15 - 2016
- [j2]Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker:
Providing fault tolerance through invasive computing. it Inf. Technol. 58(6): 309-328 (2016) - [c6]Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP 2016: 58-66 - 2015
- [j1]Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer:
Techniques for on-demand structural redundancy for massively parallel processor arrays. J. Syst. Archit. 61(10): 615-627 (2015) - [c5]Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer:
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS 2015: 1-8 - [c4]Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting:
Adaptive fault tolerance through invasive computing. AHS 2015: 1-8 - [c3]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari:
On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP 2015: 194-201 - [c2]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE 2015: 188-197 - 2014
- [c1]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic inner loop parallelisation for massively parallel processor arrays. MEMOCODE 2014: 219-228
Coauthor Index
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