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ORCIDJorge Echavarria
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Books and Theses
- 2022
[b1]Jorge Alfonso Echavarria Gutiérrez:
On the Approximation of Arithmetic Functions and Logic Synthesis of Approximate Very Large Boolean Networks. University of Erlangen-Nuremberg, Germany, 2022
Journal Articles
- 2022
- [j3]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher
, Jürgen Teich:
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. 64(3): 89-98 (2022) - 2021
- [j2]Jorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido, Claudia Feregrino Uribe:
IP-cores watermarking scheme at behavioral level using genetic algorithms. Eng. Appl. Artif. Intell. 104: 104386 (2021) - 2018
- [j1]Jorge Echavarria, Stefan Wildermann, Eduard Potwigin, Jürgen Teich:
Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders. IEEE Embed. Syst. Lett. 10(2): 37-40 (2018)
Conference and Workshop Papers
- 2024
- [c12]Martin Schulz, Hossam Ahmed, Xiaolong Deng, Jorge Echavarria, Mathias Gammelmark, Sven Karlsson, Ercüment Kaya, Michal Reznak, Laura Brandon Schulz, Matthew Tovey:
From the Physics Lab to the Computer Lab: Towards Flexible and Comprehensive DevOps for Quantum Computing. CF (Companion) 2024 - 2021
- [c11]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
Approximate Logic Synthesis of Very Large Boolean Networks. DATE 2021: 1552-1557 - [c10]Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels:
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. ETS 2021: 1-10 - [c9]Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, Ian O'Connor:
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. ICCAD 2021: 1-9 - 2020
- [c8]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich:
Probabilistic Error Propagation through Approximated Boolean Networks. DAC 2020: 1-6 - 2018
- [c7]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs. FPT 2018: 326-329 - [c6]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
Design space exploration of multi-output logic function approximations. ICCAD 2018: 52 - [c5]Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Can Approximate Computing Reduce Power Consumption on FPGAs? ICECS 2018: 841-844 - 2017
- [c4]Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich, Stefan Wildermann:
Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. SCOPES 2017: 89-92 - 2016
- [c3]Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich:
A LUT-Based Approximate Adder. FCCM 2016: 27 - [c2]Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener:
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT 2016: 213-216 - 2014
- [c1]Jorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido:
FSM merging and reduction for IP cores watermarking using Genetic Algorithms. ReConFig 2014: 1-7
Informal and Other Publications
- 2021
- [i1]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR abs/2105.05588 (2021)
Coauthor Index
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