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Austin Rovinski
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2020 – today
- 2024
- [i1]Bing-Yue Wu, Utsav Sharma, Sai Rahul Dhanvi Kankipati, Ajay Yadav, Bintu Kappil George, Sai Ritish Guntupalli, Austin Rovinski, Vidya A. Chhabria:
EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD. CoRR abs/2405.06676 (2024) - 2020
- [j4]Dong-Hyeon Park
, Subhankar Pal
, Siying Feng
, Paul Gao, Jielun Tan, Austin Rovinski
, Shaolin Xie
, Chun Zhao
, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont
, Kuan-Yu Chen
, Chaitali Chakrabarti, Michael Bedford Taylor
, Trevor N. Mudge, David T. Blaauw
, Hun-Seok Kim
, Ronald G. Dreslinski:
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. IEEE J. Solid State Circuits 55(4): 933-944 (2020) - [c7]Austin Rovinski, Tutu Ajayi, Minsoo Kim, Guanru Wang, Mehdi Saligane:
Bridging Academic Open-Source EDA to Real-World Usability. ICCAD 2020: 111:1-111:7 - [c6]Xin He, Subhankar Pal
, Aporva Amarnath, Siying Feng
, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Kuan-Yu Chen, Ronald G. Dreslinski, Trevor N. Mudge:
Sparse-TPU: adapting systolic arrays for sparse matrices. ICS 2020: 19:1-19:12
2010 – 2019
- 2019
- [c5]Austin Rovinski, Chun Zhao
, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang
, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski:
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits 2019: 30- - [c4]Subhankar Pal
, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao
, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen
, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski:
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. VLSI Circuits 2019: 150- - 2018
- [j3]Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao
, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang
, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor:
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. IEEE Micro 38(2): 30-41 (2018) - 2017
- [c3]Yiping Kang, Johann Hauswald, Cao Gao, Austin Rovinski, Trevor N. Mudge, Jason Mars, Lingjia Tang:
Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge. ASPLOS 2017: 615-629 - [c2]Aporva Amarnath, Siying Feng
, Subhankar Pal
, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski:
A carbon nanotube transistor based RISC-V processor using pass transistor logic. ISLPED 2017: 1-6 - 2016
- [j2]Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Cheng Li, Austin Rovinski, Arjun Khurana, Ronald G. Dreslinski, Trevor N. Mudge, Vinicius Petrucci, Lingjia Tang, Jason Mars:
Sirius Implications for Future Warehouse-Scale Computers. IEEE Micro 36(3): 42-53 (2016) - [j1]Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Hailong Yang, Yiping Kang, Cheng Li, Austin Rovinski, Arjun Khurana, Ronald G. Dreslinski, Trevor N. Mudge, Vinicius Petrucci, Lingjia Tang, Jason Mars:
Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant. ACM Trans. Comput. Syst. 34(1): 2:1-2:32 (2016) - 2015
- [c1]Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Cheng Li, Austin Rovinski, Arjun Khurana, Ronald G. Dreslinski, Trevor N. Mudge, Vinicius Petrucci, Lingjia Tang, Jason Mars:
Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers. ASPLOS 2015: 223-238
Coauthor Index
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last updated on 2024-06-14 19:02 CEST by the dblp team
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