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ORCIDJakub Podivinsky
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2020 – today
- 2024
[b1]Jakub Podivinsky:
Využití verifikace pro ověřování odolnosti proti poruchám u systémů založených na FPGA ; Use of verification for testing fault-tolerance in FPGA-based system. Brno University of Technology, Czech Republic, 2024- 2021
- [c28]Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. DSD 2021: 553-556 - [c27]Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. LATS 2021: 1-6 - 2020
- [c26]Jakub Lojda, Jakub Podivinsky, Ondrej Cekan
, Richard Panek, Martin Krcma, Zdenek Kotásek:
Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. DDECS 2020: 1-4 - [c25]Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. DSD 2020: 680-683 - [c24]Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. EWDTS 2020: 1-5 - [c23]Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek:
Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination. LASCAS 2020: 1-4 - [c22]Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. LASCAS 2020: 1-4 - [c21]Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [c20]Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek:
Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. DSD 2019: 506-513 - [c19]Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek:
Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. DSD 2019: 597-600 - [c18]Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. LATS 2019: 1-4 - [c17]Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek:
Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. LATS 2019: 1-4 - 2018
- [c16]Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek:
Program Generation Through a Probabilistic Constrained Grammar. DSD 2018: 214-220 - [c15]Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek:
Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller. DSD 2018: 229-236 - [c14]Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek:
FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. DSD 2018: 244-251 - [c13]Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. EWDTS 2018: 1-7 - [c12]Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. EWDTS 2018: 1-6 - [c11]Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek:
An Experimental Evaluation of Fault-Tolerant FPGA-Based Robot Controller. EWDTS 2018: 1-7 - 2017
- [j2]Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Marcela Zachariásová, Martin Krcma, Zdenek Kotásek:
Functional verification based platform for evaluating fault tolerance properties. Microprocess. Microsystems 52: 145-159 (2017) - [c10]Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek:
Reliability Analysis and Improvement of FPGA-Based Robot Controller. DSD 2017: 337-344 - [c9]Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation. EWDTS 2017: 1-6 - [c8]Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek, Martin Krcma:
Data types and operations modifications: A practical approach to fault tolerance in HLS. EWDTS 2017: 1-6 - 2016
- [c7]Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek:
Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems. DSD 2016: 487-494 - [c6]Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek:
Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs. FPT 2016: 293-294 - [c5]Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek:
Random stimuli generation based on a stochastic context-free grammar. FPT 2016: 295-296 - [c4]Jakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek:
HLS-based fault tolerance approach for SRAM-based FPGAs. FPT 2016: 301-302 - 2015
- [j1]Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek:
The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications. Microprocess. Microsystems 39(8): 1215-1230 (2015) - [c3]Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek:
FPGA Prototyping and Accelerated Verification of ASIPs. DDECS 2015: 145-148 - [c2]Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek:
Software Fault Tolerance: The Evaluation by Functional Verification. DSD 2015: 284-287 - 2014
- [c1]Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek:
The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications. DSD 2014: 312-319
Coauthor Index
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last updated on 2024-11-15 20:39 CET by the dblp team
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