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ORCIDGul N. Khan
Person information
- affiliation: Toronto Metropolitan University, Canada
- affiliation (2000 - 2001): University of Saskatchewan, Canada
- affiliation (1997 - 2000): Nanyang Technological University, Singapore
- affiliation (PhD 1989): Imperial College London, UK
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Books and Theses
- 1989
[b1]Gul Nawaz Khan:
Machine vision for endoscope control and navigation. Imperial College London, UK, 1989
Journal Articles
- 2021
- [j17]Daniel Junehee Lee, Fei Yuan, Gul N. Khan
, Yushi Zhou:
An 8-bit digital-to-time converter with pre-skewing and time interpolation. IET Circuits Devices Syst. 15(7): 670-685 (2021) - 2020
- [j16]Masoud Oveis Gharan, Gul N. Khan:
Reconfigurable on-chip interconnection networks for high performance embedded SoC design. J. Syst. Archit. 106: 101711 (2020) - 2017
- [j15]Muhammad Obaidullah, Gul N. Khan:
Application mapping to mesh NoCs using a Tabu-search based swarm optimization. Microprocess. Microsystems 55: 13-25 (2017) - 2016
- [j14]Masoud Oveis Gharan, Gul N. Khan:
Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 465-478 (2016) - 2015
- [j13]Masoud Oveis Gharan, Gul N. Khan:
Statically adaptive multi FIFO buffer architecture for network on chip. Microprocess. Microsystems 39(1): 11-26 (2015) - [j12]Gul N. Khan, Markus B. Moessner:
Low-cost authentication protocol for passive, computation capable RFID tags. Wirel. Networks 21(2): 565-580 (2015) - 2013
- [j11]Anita Tino, Gul N. Khan:
High performance NoC synthesis using analytical modeling and simulation with optimal power and minimal IC area. J. Syst. Archit. 59(10-D): 1348-1363 (2013) - 2012
- [j10]Markus B. Moessner, Gul N. Khan:
Secure authentication scheme for passive C1G2 RFID tags. Comput. Networks 56(1): 273-286 (2012) - [j9]Omesh Mutukuda, Andy Gean Ye, Gul N. Khan:
Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs. Microprocess. Microsystems 36(3): 167-175 (2012) - 2011
- [j8]Anita Tino, Gul N. Khan:
Designing power and performance optimal application-specific Network-on-Chip architectures. Microprocess. Microsystems 35(6): 523-534 (2011) - 2010
- [j7]Gul N. Khan, Victor Dumitriu:
A modeling tool for simulating and design of on-chip network systems. Microprocess. Microsystems 34(2-4): 84-95 (2010) - 2009
- [j6]Yong Chen, Fei Yuan, Gul N. Khan:
A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification. Microelectron. J. 40(10): 1496-1501 (2009) - [j5]Victor Dumitriu, Gul N. Khan:
Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1433-1446 (2009) - 2008
- [j4]Gul N. Khan, Usman Ahmed:
CAD tool for hardware software co-synthesis of heterogeneous multiple processor embedded architectures. Des. Autom. Embed. Syst. 12(4): 313-343 (2008) - 1996
- [j3]Gul N. Khan, Duncan Fyfe Gillies:
Vision based navigation system for an endoscope. Image Vis. Comput. 14(10): 763-772 (1996) - 1994
- [j2]Gul N. Khan, Khalid Mahmud, M. Salman Igbal, Haroon-Ur-Rashid Khan:
RSM - a restricted shared memory architecture for high speed interprocessor communication. Microprocess. Microsystems 18(4): 193-203 (1994) - 1992
- [j1]Gul N. Khan, Duncan Fyfe Gillies:
Extracting contours by perceptual grouping. Image Vis. Comput. 10(2): 77-88 (1992)
Conference and Workshop Papers
- 2023
- [c44]Sunbal Cheema, Gul N. Khan:
GPU Auto-tuning Framework for Optimal Performance and Power Consumption. GPGPU@PPoPP 2023: 1-6 - 2020
- [c43]Sunbal Cheema, Gul N. Khan:
Power and Performance Analysis of Deep Neural Networks for Energy-aware Heterogeneous Systems. SMC 2020: 2184-2189 - 2019
- [c42]Gul N. Khan, Masoud Oveis Gharan:
Application Specific Reconfigurable SoC Interconnection Network Architecture. ARCS 2019: 322-333 - [c41]Abdullah Siddiqui, Gul N. Khan:
Design Space Exploration of Embedded Applications on Heterogeneous CPU-GPU Platforms. HPCS 2019: 620-627 - [c40]Daniel Junehee Lee, Fei Yuan, Gul N. Khan:
Digitally Interpolated Pre-Skewed Delay-Line Digital-to-Time Converter with Minimum Nonlinearity and Latency. MWSCAS 2019: 892-895 - 2018
- [c39]Masoud Oveis Gharan, Gul N. Khan:
Flexible Reconfigurable On-chip Networks for Multi-core SoCs. HEART 2018: 19:1-19:6 - [c38]Muhammad Obaidullah, Gul N. Khan, Fei Yuan:
Multi-Swarm based NoC Configuration and Synthesis. NORCAS 2018: 1-6 - 2017
- [c37]Gul N. Khan, Stephen Chui:
Congestion Aware Routing for On-Chip Communication in NoC Systems. CISIS 2017: 547-556 - [c36]Muhammad Obaidullah, Gul N. Khan:
Optimal application mapping to 2D-mesh NoCs by using a tabu-based particle swarm methodology. AISTECS@HiPEAC 2017: 17-22 - [c35]Muhammad Obaidullah, Gul N. Khan:
Hybrid multi-swarm optimization based NoC synthesis. SoCC 2017: 62-67 - 2016
- [c34]Masoud Oveis Gharan, Gul N. Khan:
Dynamic virtual channel and index-based arbitration based Network on Chip router architecture. HPCS 2016: 96-103 - [c33]Masoud Oveis Gharan, Gul N. Khan:
Adaptive VC Organization and Arbitration for Efficient NoC Design. MCSoC 2016: 31-38 - 2015
- [c32]Masoud Oveis Gharan, Gul N. Khan:
Index-Based Round-Robin Arbiter for NoC Routers. ISVLSI 2015: 62-67 - [c31]Masoud Oveis Gharan, Gul N. Khan:
Dynamic VC Organization for Efficient NoC Communication. MCSoC 2015: 151-158 - 2014
- [c30]Masoud Oveis Gharan, Gul N. Khan:
Dynamic Virtual Channel Configuration for Efficient Multicore Systems. CISIS 2014: 445-450 - [c29]Masoud Oveis Gharan, Gul N. Khan:
Packet-based Adaptive Virtual Channel Configuration for NoC Systems. FNC/MobiSPC 2014: 552-558 - [c28]Mohammed J. Hakeem, Kaamran Raahemifar, Gul N. Khan:
Novel modulo based Aloha anti-collision algorithm for RFID systems. IEEE RFID 2014: 97-102 - [c27]Masoud Oveis Gharan, Gul N. Khan:
Efficient Virtual Channel Organization and Congestion Avoidance in Multicore NoC Systems. SBAC-PAD (Workshops) 2014: 30-35 - [c26]Masoud Oveis Gharan, Gul N. Khan:
Power and chip-area aware network-on-chip modeling for system on chip simulation. SimuTools 2014: 178-185 - 2013
- [c25]Anita Tino, Gul N. Khan, Fei Yuan:
Hardware realization of GALS based cortical column systems. AHS 2013: 144-149 - [c24]Mohammed J. Hakeem, Kaamran Raahemifar, Gul N. Khan:
HPAP: A novel authentication scheme for RFID systems. CCECE 2013: 1-6 - [c23]Guangyu Zhu, Gul N. Khan:
Symmetric key based RFID authentication protocol with a secure key-updating scheme. CCECE 2013: 1-5 - [c22]Gul N. Khan, Guangyu Zhu:
Secure RFID Authentication Protocol with Key Updating Technique. ICCCN 2013: 1-5 - [c21]Anita Tino, Gul N. Khan, Fei Yuan:
Towards Hardware Realizations of Intelligent Systems: A Cortical Column Approach. ICPP 2013: 492-497 - [c20]Mohammed J. Hakeem, Kaamran Raahemifar, Gul N. Khan:
A novel key management protocol for RFID systems. IWCMC 2013: 1107-1113 - [c19]Gul N. Khan, M. Zulfiker Ali:
Password based Secure Authentication Methodology for Wireless Sensor Network. PECCS 2013: 35-41 - 2012
- [c18]Gul N. Khan, Anita Tino:
Synthesis of NoC Interconnects for Multi-core Architectures. CISIS 2012: 432-437 - [c17]Gul N. Khan, Anita Tino:
Synthesis of NoC Interconnects for Custom MPSoC Architectures. NOCS 2012: 75-82 - 2011
- [c16]Jack Yu, Gul N. Khan, Fei Yuan:
XTEA encryption based novel RFID security protocol. CCECE 2011: 58-62 - [c15]Masoud Oveis Gharan, Gul N. Khan:
Flexible simulation and modeling for 2D topology NoC system design. CCECE 2011: 180-185 - [c14]Anita Tino, Gul N. Khan:
Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures. DATE 2011: 485-490 - [c13]Gul N. Khan, Markus B. Moessner:
Secure Authentication Protocol for RFID Systems. ICCCN 2011: 1-7 - [c12]Gul N. Khan, Jack Yu, Fei Yuan:
XTEA Based Secure Authentication Protocol for RFID Systems. ICCCN 2011: 1-6 - 2010
- [c11]Omesh Mutukuda, Andy Gean Ye, Gul N. Khan:
The effect of multi-bit based connections on the area efficiency of FPGAs utilizing unidirectional routing resources. FPT 2010: 216-223 - [c10]Anita Tino, Gul N. Khan:
Power and Performance Tabu Search Based Multicore Network-on-Chip Design. ICPP Workshops 2010: 74-81 - 2009
- [c9]Gul N. Khan, Victor Dumitriu:
Throughput-based network-on-chip topology generation and analysis. CCECE 2009: 180-184 - [c8]Gul N. Khan, Anika Awwal:
Codesign of Embedded Systems with Process/Module Level Real-Time Deadlines. CSE (2) 2009: 526-531 - [c7]Gul N. Khan, Victor Dumitriu:
Simulation environment for design and verification of Network-on-Chip and multi-core systems. MASCOTS 2009: 1-9 - 2007
- [c6]Gul N. Khan, Usman Ahmed:
Hardware-Software Cosynthesis of Multiprocessor Embedded Architectures. AINA Workshops (1) 2007: 804-810 - [c5]Rushin Shojaii, Javad Alirezaie, Gul N. Khan, Paul S. Babyn:
Automatic honeycomb lung segmentation in pediatric ct images. ISSPA 2007: 1-4 - 2006
- [c4]Gul N. Khan, Jacob Levman, Javad Alirezaie:
Hardware-Software Co-Synthesis of Heterogeneous Embedded Computer Systems. CCECE 2006: 1304-1307 - 2003
- [c3]Matthew Jin, Gul N. Khan:
Heterogeneous Hardware-Software System Partitioning using Extended Directed Acyclic Graph. PDCS 2003: 181-186 - 2000
- [c2]Suliman Al-Hawamdeh, Gul N. Khan:
Content Based Indexing and Retrieval in a Digital Library of Arabic Scripts and Calligraphy. ECDL 2000: 14-23 - 1998
- [c1]Gul N. Khan:
Fault-tolerant architecture for high performance embedded system applications. ICCD 1998: 384-389
Coauthor Index
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last updated on 2024-05-08 23:26 CEST by the dblp team
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