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Journal Articles
- 2016
[j3]Tsung-Han Tsai, Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, Hsin-Shu Chen
:
An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(5): 683-692 (2016)- [j2]Yao-Sheng Hu, Po-Chao Huang, Hung-Yen Tai, Hsin-Shu Chen:
A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1166-1170 (2016) - 2014
- [j1]Hung-Yen Tai, Cheng-Hsueh Tsai, Pao-Yang Tsai, Hung-Wei Chen, Hsin-Shu Chen:
A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 61-II(5): 339-343 (2014)
Conference and Workshop Papers
- 2020
- [c5]Hsin-Shu Chen, Sheng-Hsiang Huang, Hung-Yen Tai, Sen-Wei Lin, Shih-Wei Wu:
A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration. ISCAS 2020: 1-4 - 2016
- [c4]Po-Chao Huang, Yao-Sheng Hu, Hung-Yen Tai, Hsin-Shu Chen:
An 8-bit 900MS/S two-step SAR ADC. ISCAS 2016: 2898 - 2014
- [c3]Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen:
A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS. A-SSCC 2014: 81-84 - [c2]Hung-Yen Tai, Yao-Sheng Hu, Hung-Wei Chen, Hsin-Shu Chen:
11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS. ISSCC 2014: 196-197 - 2012
- [c1]Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen:
A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS. VLSIC 2012: 92-93
Coauthor Index
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