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ORCIDDogan Ulus
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- affiliation: Bogazici University, Istanbul, Turkey
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2020 – today
- 2024
[j3]Dogan Ulus
, Thomas Ferrère, Eugene Asarin, Dejan Nickovic, Oded Maler:
Elements of Timed Pattern Matching. ACM Trans. Embed. Comput. Syst. 23(4): 59:1-59:45 (2024)- [i5]Ali Mehran, Dogan Ulus:
Runtime Verification Containers for Publish/Subscribe Networks. CoRR abs/2408.06380 (2024) - 2021
- [c18]Eugene Asarin, Thomas Ferrère, Dejan Nickovic, Dogan Ulus:
On the Complexity of Timed Pattern Matching. FORMATS 2021: 15-31 - 2020
- [j2]Klaus Havelund, Doron Peled, Dogan Ulus:
First-order temporal logic monitoring with BDDs. Formal Methods Syst. Des. 56(1): 1-21 (2020) - [j1]Dejan Nickovic, Olivier Lebeltel, Oded Maler, Thomas Ferrère, Dogan Ulus:
AMT 2.0: qualitative and quantitative trace analysis with extended signal temporal logic. Int. J. Softw. Tools Technol. Transf. 22(6): 741-758 (2020)
2010 – 2019
- 2019
- [c17]Dogan Ulus, Calin Belta:
Reactive Control Meets Runtime Verification: A Case Study of Navigation. RV 2019: 368-374 - [c16]Dogan Ulus:
Timescales: A Benchmark Generator for MTL Monitoring Tools. RV 2019: 402-412 - [i4]Dogan Ulus:
Online Monitoring of Metric Temporal Logic using Sequential Networks. CoRR abs/1901.00175 (2019) - [i3]Dogan Ulus, Calin Belta:
Reactive Control Meets Runtime Verification: A Case Study of Navigation. CoRR abs/1902.04024 (2019) - 2018
- [b1]Dogan Ulus:
Pattern Matching with Time : Theory and Applications. (Filtrage par motif temporisé : Théorie et Applications). Grenoble Alpes University, France, 2018 - [c15]Klaus Havelund, Doron Peled, Dogan Ulus:
DejaVu: A Monitoring Tool for First-Order Temporal Logic. MT@CPSWeek 2018: 12-13 - [c14]Houssam Abbas, Indranil Saha, Yasser Shoukry, Rüdiger Ehlers, Georgios Fainekos, Rajesh Gupta, Rupak Majumdar, Dogan Ulus:
Embedded software for robotics: challenges and future directions: special session. EMSOFT 2018: 10 - [c13]Dogan Ulus, Oded Maler:
Specifying Timed Patterns using Temporal Logic. HSCC 2018: 167-176 - [c12]Dejan Nickovic, Olivier Lebeltel, Oded Maler, Thomas Ferrère, Dogan Ulus:
AMT 2.0: Qualitative and Quantitative Trace Analysis with Extended Signal Temporal Logic. TACAS (2) 2018: 303-319 - [i2]Dogan Ulus:
Sequential Circuits from Regular Expressions Revisited. CoRR abs/1801.08979 (2018) - 2017
- [c11]Rajeev Alur, Konstantinos Mamouras, Dogan Ulus:
Derivatives of Quantitative Regular Expressions. Models, Algorithms, Logics and Tools 2017: 75-95 - [c10]Dogan Ulus:
Montre: A Tool for Monitoring Timed Regular Expressions. CAV (1) 2017: 329-335 - [c9]Klaus Havelund, Doron Peled, Dogan Ulus:
First order temporal logic monitoring with BDDs. FMCAD 2017: 116-123 - [c8]Alexey Bakhirkin, Thomas Ferrère, Oded Maler, Dogan Ulus:
On the Quantitative Semantics of Regular Expressions over Real-Valued Signals. FORMATS 2017: 189-206 - [c7]Eugene Asarin, Oded Maler, Dejan Nickovic, Dogan Ulus:
Combining the Temporal and Epistemic Dimensions for MTL Monitoring. FORMATS 2017: 207-223 - 2016
- [c6]Dogan Ulus, Thomas Ferrère, Eugene Asarin, Oded Maler:
Online Timed Pattern Matching Using Derivatives. TACAS 2016: 736-751 - [i1]Dogan Ulus:
Montre: A Tool for Monitoring Timed Regular Expressions. CoRR abs/1605.05963 (2016) - 2015
- [c5]Thomas Ferrère, Oded Maler, Dejan Nickovic, Dogan Ulus:
Measuring with Timed Patterns. CAV (2) 2015: 322-337 - 2014
- [c4]Dogan Ulus, Thomas Ferrère, Eugene Asarin, Oded Maler:
Timed Pattern Matching. FORMATS 2014: 222-236 - 2013
- [c3]Dogan Ulus, Alper Sen, I. Faik Baskaya:
Integrating circuit analyses for assertion-based verification of programmable AMS circuits. FDL 2013: 1-8 - [c2]Dogan Ulus, Alper Sen, I. Faik Baskaya:
Analog layer extensions for analog/mixed-signal assertion languages. VLSI-SoC 2013: 66-71 - 2012
- [c1]Dogan Ulus, Alper Sen:
Using haloes in mixed-signal assertion based verification. HLDVT 2012: 49-55
Coauthor Index
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last updated on 2024-09-25 01:37 CEST by the dblp team
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