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2010 – 2019
- 2019
[j5]Swarnil Roy
, Sagar Mukherjee, Arka Dutta, Chandan Kumar Sarkar, Chayanika Bose:
Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application. IET Circuits Devices Syst. 13(3): 337-343 (2019)- 2018
- [j4]Sagar Mukherjee, Arka Dutta, Swarnil Roy, Chandan Kumar Sarkar:
Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET. IEEE Trans. Circuits Syst. II Express Briefs 65-II(7): 844-848 (2018) - 2016
- [j3]Sagar Mukherjee, Kalyan Koley, Arka Dutta, Chandan Kumar Sarkar:
Low-power amplitude modulator for wireless application using underlap double-gate metal-oxide-semiconductor field-effect transistor. IET Circuits Devices Syst. 10(3): 201-208 (2016) - [j2]Sagar Mukherjee, Swarnil Roy, Arka Dutta, Chandan Kumar Sarkar:
Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance. IET Circuits Devices Syst. 10(6): 497-503 (2016) - 2015
- [j1]Sagar Mukherjee, Arka Dutta, Swarnil Roy, Kalyan Koley, Chandan Kumar Sarkar:
Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET. Microelectron. J. 46(11): 1082-1090 (2015) - 2013
- [i2]Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Chandan Kumar Sarkar:
A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme. CoRR abs/1309.7163 (2013) - [i1]Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar:
Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit. CoRR abs/1310.3203 (2013) - 2012
- [c2]Sagar Mukherjee, Dipankar Saha, Posiba Mostafa, Sayan Chatterjee, Chandan Kumar Sarkar:
A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications. ISED 2012: 28-32 - [c1]Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar:
Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. ISED 2012: 130-134
Coauthor Index
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