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Dustin Peterson
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2010 – 2019
- 2019
- [c10]Dustin Peterson, Oliver Bringmann:
Fully-automated synthesis of power management controllers from UPF. ASP-DAC 2019: 76-81 - [c9]Dustin Peterson, Oliver Bringmann:
Power-Gating Models for Rapid Design Exploration. NEWCAS 2019: 1-4 - 2018
- [c8]Dustin Peterson, Yannick Boekle, Oliver Bringmann:
Detecting non-functional circuit activity in SoC designs. ASP-DAC 2018: 464-469 - 2016
- [c7]Dustin Peterson, Oliver Bringmann:
SMoSi: A framework for the derivation of sleep mode traces from RTL simulations. ASP-DAC 2016: 330-335 - [c6]Konstantin Lübeck, David Morgenstern, Thomas Schweizer, Dustin Peterson, Wolfgang Rosenstiel, Oliver Bringmann:
Neues Konzept zur Steigerung der Zuverlässigkeit einer ARM-basierten Prozessorarchitektur unter Verwendung eines CGRAs. MBMV 2016: 46-58 - 2015
- [c5]Johannes Maximilian Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel:
Spatial and temporal granularity limits of body biasing in UTBB-FDSOI. DATE 2015: 876-879 - [c4]Sebastian Matthias Burg, Dustin Peterson, Oliver Bringmann:
End-to-Display Encryption: A Pixel-Domain Encryption with Security Benefit. IH&MMSec 2015: 123-128 - 2013
- [c3]Thomas Schweizer, Dustin Peterson, Johannes Maximilian Kühn, Tommy Kuhn, Wolfgang Rosenstiel:
A Fast and Accurate FPGA-Based Fault Injection System. FCCM 2013: 236 - [c2]Dustin Peterson, Oliver Bringmann, Thomas Schweizer, Wolfgang Rosenstiel:
StML: Bridging the gap between FPGA design and HDL circuit description. FPT 2013: 278-285 - [c1]Johannes Maximilian Kühn, Thomas Schweizer, Dustin Peterson, Tommy Kuhn, Wolfgang Rosenstiel:
Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection. FPT 2013: 462-465
Coauthor Index
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