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ORCIDYeonho Lee 0002
Person information
- affiliation: SK Hynix Inc., Icheon, South Korea
- affiliation (PhD 2019): Korea University, Department of Electrical Engineering, Seoul, South Korea
Other persons with the same name
- Yeonho Lee 0001
![[0009-0006-7331-3501]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0009-0006-7331-3501")
— Sungkyunkwan University, Suwon, South Korea
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Journal Articles
- 2023
[j10]Myeong-Jae Park, Jinhyung Lee, Kyungjun Cho, Ji Hwan Park, Junil Moon, Sung-Hak Lee, Tae-Kyun Kim, Sanghoon Oh, Seokwoo Choi, Yongsuk Choi, Ho Sung Cho, Tae-Sik Yun, Young Jun Koo, Jae-Seung Lee, Byung Kuk Yoon, Young-Jun Park, Sangmuk Oh, Chang Kwon Lee, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun Lim, Kyo Yun Lee, Sang-Hoon Lee, Woo Sung We, Seungchan Kim, Seung Min Yang, Keonho Lee, In-Keun Kim, Younghyun Jeon, Jae-Hyung Park, Jong Chan Yun, Seonyeol Kim, Dong-Yeol Lee, Su-Hyun Oh, Junghyun Shin, Yeonho Lee, Jieun Jang, Joohwan Cho:
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. IEEE J. Solid State Circuits 58(1): 256-269 (2023)- 2022
- [j9]Jincheol Sim, Yeonho Lee, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim:
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 404-408 (2022) - 2021
- [j8]Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Chulwoo Kim:
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector. IEEE Access 9: 118907-118918 (2021) - [j7]Yoonjae Choi, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Chulwoo Kim:
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(10): 3189-3193 (2021) - 2019
- [j6]Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim:
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. IEEE J. Solid State Circuits 54(2): 463-475 (2019) - [j5]Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim:
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 192-196 (2019) - 2018
- [j4]Jeongsik Yoo, Yeonho Lee, Yoonjae Choi, Hyunsu Park, Sanghune Park, Chulwoo Kim:
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX. IEEE Trans. Circuits Syst. II Express Briefs 65-II(6): 789-793 (2018) - [j3]Jaehun Jun, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim:
A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1509-1513 (2018) - 2017
- [j2]Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim:
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(10): 2691-2702 (2017) - 2016
- [j1]Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim:
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1092-1103 (2016)
Conference and Workshop Papers
- 2024
- [c4]Jinhyung Lee, Kyungjun Cho, Chang Kwon Lee, Yeonho Lee, Jae-Hyung Park, Su-Hyun Oh, Yucheon Ju, Chunseok Jeong, Ho Sung Cho, Jaeseung Lee, Tae-Sik Yun, Jin Hee Cho, Sangmuk Oh, Junil Moon, Young-Jun Park, Hong-Seok Choi, In-Keun Kim, Seung Min Yang, Sun-Yeol Kim, Jaemin Jang, Jinwook Kim, Seong-Hee Lee, Younghyun Jeon, Juhyung Park, Tae-Kyun Kim, Dongyoon Ka, Sanghoon Oh, Jinse Kim, Junyeol Jeon, Seonhong Kim, Kyeong Tae Kim, Taeho Kim, Hyeonjin Yang, Dongju Yang, Minseop Lee, Heewoong Song, Dongwook Jang, Junghyun Shin, Hyunsik Kim, Chang-Ki Baek, Hajun Jeong, Jongchan Yoon, Seung-Kyun Lim, Kyo Yun Lee, Young Jun Koo, Myeong-Jae Park, Joohwan Cho, Jonghwan Kim:
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization. ISSCC 2024: 238-240 - 2019
- [c3]Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim:
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface. ISSCC 2019: 382-384 - 2018
- [c2]Yeonho Lee, Yoonjae Choi, Chulwoo Kim:
12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. ASP-DAC 2018: 287-288 - 2017
- [c1]Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim:
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. ISSCC 2017: 490-491
Coauthor Index
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