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Ravi Tej Uppu

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2010 – 2019

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2014
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Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian:
Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. VLSID 2014: 133-138
2013
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Ravi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee:
A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. VLSI Design 2013: 109-114

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