"A High Throughput Multiplier Design Exploiting Input Based Statistical ..."

Ravi Tej Uppu et al. (2013)

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DOI: 10.1109/VLSID.2013.172

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Ravi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee:
A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. VLSI Design 2013: 109-114

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