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Sheng-Han Yeh

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2010 – 2019

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2015
[j4]
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Shang-Tsung Yu, Sheng-Han Yeh, Tsung-Yi Ho:
Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 529-539 (2015)
2014
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Sheng-Han Yeh, Jia-Wen Chang, Tsung-Wei Huang, Shang-Tsung Yu, Tsung-Yi Ho:
Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1302-1315 (2014)
[c2]
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Shang-Tsung Yu, Sheng-Han Yeh, Tsung-Yi Ho:
Reliability-driven chip-level design for high-frequency digital microfluidic biochips. ISPD 2014: 133-140
2013
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Jia-Wen Chang, Sheng-Han Yeh, Tsung-Wei Huang, Tsung-Yi Ho:
Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 216-227 (2013)
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Jia-Wen Chang, Sheng-Han Yeh, Tsung-Wei Huang, Tsung-Yi Ho:
An ILP-Based Routing Algorithm for Pin-Constrained EWOD Chips With Obstacle Avoidance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1655-1667 (2013)
2012
[c1]
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Sheng-Han Yeh, Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho:
Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips. ICCAD 2012: 353-360

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