default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDTosiron Adegbija
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
Journal Articles
- 2024
[j17]Alaba Yusuf
, Tosiron Adegbija, Dhruv Gajaria:
Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey. IEEE Access 12: 28036-28056 (2024)- [j16]Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija:
STT-RAM-Based Hierarchical in-Memory Computing. IEEE Trans. Parallel Distributed Syst. 35(9): 1615-1629 (2024) - 2023
- [j15]Ilkin Aliyev, Kama Svoboda, Tosiron Adegbija:
Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4): 1062-1072 (2023) - 2022
- [j14]Dhruv Gajaria, Tosiron Adegbija:
Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads. Future Gener. Comput. Syst. 136: 231-240 (2022) - [j13]Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
A high-level synthesis approach for precisely-timed, energy-efficient embedded systems. Sustain. Comput. Informatics Syst. 35: 100741 (2022) - [j12]Dhruv Gajaria, Tosiron Adegbija:
Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing. J. Signal Process. Syst. 94(6): 559-577 (2022) - 2021
- [j11]Ankur Limaye, Antonino Tumeo, Tosiron Adegbija:
Energy characterization of graph workloads. Sustain. Comput. Informatics Syst. 29(Part): 100465 (2021) - 2020
- [j10]Chenxi Dai, Tosiron Adegbija:
CONDENSE: A Moving Target Defense Approach for Mitigating Cache Side-Channel Attacks. IEEE Consumer Electron. Mag. 9(3): 114-120 (2020) - [j9]Kyle Kuan, Tosiron Adegbija:
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1328-1339 (2020) - [j8]Renato Cordeiro, Dhruv Gajaria, Ankur Limaye, Tosiron Adegbija, Nima Karimian, Fatemeh Tehranipoor:
ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3373-3384 (2020) - [j7]Keeley Criswell, Tosiron Adegbija:
A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior. IEEE Trans. Parallel Distributed Syst. 31(1): 224-236 (2020) - 2019
- [j6]Kyle Kuan, Tosiron Adegbija:
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. IEEE Trans. Computers 68(11): 1623-1634 (2019) - 2018
- [j5]Tosiron Adegbija, Ann Gordon-Ross:
TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems. Comput. 7(1): 3 (2018) - [j4]Ankur Limaye, Tosiron Adegbija:
HERMIT: A Benchmark Suite for the Internet of Medical Things. IEEE Internet Things J. 5(5): 4212-4222 (2018) - [j3]Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, Ann Gordon-Ross:
Microprocessor Optimizations for the Internet of Things: A Survey. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 7-20 (2018) - [j2]Tosiron Adegbija, Ann Gordon-Ross:
PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 110-121 (2018) - 2014
- [j1]Tosiron Adegbija, Ann Gordon-Ross, Arslan Munir:
Phase distance mapping: a phase-based cache tuning methodology for embedded systems. Des. Autom. Embed. Syst. 18(3-4): 251-278 (2014)
Conference and Workshop Papers
- 2024
- [c37]Dhruv Gajaria, Tosiron Adegbija, Kevin Antony Gomez:
CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing. ASAP 2024: 228-236 - [c36]Ilkin Aliyev, Tosiron Adegbija:
Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks. DATE 2024: 1-2 - [c35]Yuchao Liao, Tosiron Adegbija, Roman Lysecky, Ravi Tandon:
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning. ACM Great Lakes Symposium on VLSI 2024: 170-176 - [c34]Ilkin Aliyev, Tosiron Adegbija:
PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine. ISCAS 2024: 1-5 - [c33]Garrett S. Rose, Tosiron Adegbija, Selçuk Köse:
Message from the Technical Program Chairs; ISVLSI 2024. ISVLSI 2024: xxviii-xxix - 2023
- [c32]Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace Pruning. ASP-DAC 2023: 567-572 - [c31]Tosiron Adegbija:
Jazznet: A Dataset of Fundamental Piano Patterns for Music Audio Machine Learning Research. ICASSP 2023: 1-5 - 2022
- [c30]Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija:
A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy. ICCD 2022: 685-692 - [c29]Kyle Kuan, Tosiron Adegbija:
A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation. ISVLSI 2022: 74-79 - 2021
- [c28]Ankur Limaye, Tosiron Adegbija:
DOSAGE: Generating Domain-Specific Accelerators for Resource-Constrained Computing. ISLPED 2021: 1-6 - 2020
- [c27]Kyle Kuan, Tosiron Adegbija:
A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. ICCD 2020: 247-254 - [c26]Yasuhiro Takahashi, Tosiron Adegbija, Linga Reddy Cenkeramaddi:
Message from the Technical Program Chairs iSES 2020. iSES 2020: xvi - 2019
- [c25]Kyle Kuan, Tosiron Adegbija:
MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache. ACM Great Lakes Symposium on VLSI 2019: 299-302 - [c24]Tosiron Adegbija, Roman Lysecky, Vinu Vijay Kumar:
Right-Provisioned IoT Edge Computing: An Overview. ACM Great Lakes Symposium on VLSI 2019: 531-536 - [c23]Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija:
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. IGSC 2019: 1-7 - [c22]Elnaz Tavakoli Yazdi, Ankur Limaye, Ali Akoglu, Tosiron Adegbija, Adam Buntzman:
Bit-Wise and Multi-GPU Implementations of the DNA Recombination Algorithm. HiPC 2019: 131-140 - [c21]Mohamad Hammam Alsafrjalani, Tosiron Adegbija, Lokesh Ramamoorthi:
Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems. ISQED 2019: 104-109 - [c20]Kyle Kuan, Tosiron Adegbija:
Energy and Performance Analysis of STTRAM Caches for Mobile Applications. MCSoC 2019: 257-264 - [c19]Dhruv Gajaria, Tosiron Adegbija:
ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors. MEMSYS 2019: 439-450 - 2018
- [c18]Jeremiah Pate, Tosiron Adegbija:
AMELIA: An application of the Internet of Things for aviation safety. CCNC 2018: 1-6 - [c17]Kyle Kuan, Tosiron Adegbija:
LARS: Logically adaptable retention time STT-RAM cache for embedded systems. DATE 2018: 461-466 - [c16]Mohamad Hammam Alsafrjalani, Tosiron Adegbija:
TaSaT: Thermal-Aware Scheduling and Tuning Algorithm for Heterogeneous and Configurable Embedded Systems. ACM Great Lakes Symposium on VLSI 2018: 75-80 - [c15]Ankur Limaye, Tosiron Adegbija:
A Workload Characterization of the SPEC CPU2017 Benchmark Suite. ISPASS 2018: 149-158 - [c14]Islam Badreldin, Ann Gordon-Ross, Tosiron Adegbija, Mohamad Hammam Alsafrjalani:
Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges. ISVLSI 2018: 719-725 - 2017
- [c13]Sam Gianelli, Edward Richter, Diego Jiménez, Hugo Valdez, Tosiron Adegbija, Ali Akoglu:
Application-Specific Autonomic Cache Tuning for General Purpose GPUs. ICCAC 2017: 104-113 - [c12]Tosiron Adegbija, Ravi Tandon:
Coding for Efficient Caching in Multicore Embedded Systems. ISVLSI 2017: 296-301 - [c11]Ankur Limaye, Tosiron Adegbija:
A Workload Characterization for the Internet of Medical Things (IoMT). ISVLSI 2017: 302-307 - [c10]Sam Gianelli, Tosiron Adegbija:
PACT: Priority-Aware Phase-Based Cache Tuning for Embedded Systems. ISVLSI 2017: 403-408 - [c9]Chenxi Dai, Tosiron Adegbija:
Exploiting Configurability as a Defense against Cache Side Channel Attacks. ISVLSI 2017: 495-500 - 2016
- [c8]Tosiron Adegbija:
Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems. ACM Great Lakes Symposium on VLSI 2016: 157-162 - [c7]Tosiron Adegbija, Ann Gordon-Ross:
Phase-Based Dynamic Instruction Window Optimization for Embedded Systems. ISVLSI 2016: 397-402 - 2015
- [c6]Tosiron Adegbija, Ann Gordon-Ross:
Phase-based Cache Locking for Embedded Systems. ACM Great Lakes Symposium on VLSI 2015: 115-120 - 2014
- [c5]Tosiron Adegbija, Ann Gordon-Ross:
Thermal-aware phase-based tuning of embedded systems. ACM Great Lakes Symposium on VLSI 2014: 279-284 - [c4]Tosiron Adegbija, Ann Gordon-Ross, Marisha Rawlins:
Analysis of cache tuner architectural layouts for multicore embedded systems. IPCCC 2014: 1-8 - [c3]Tosiron Adegbija, Ann Gordon-Ross:
Dynamic Phase-Based Optimization of Embedded Systems. ISVLSI 2014: 236-239 - 2013
- [c2]Tosiron Adegbija, Ann Gordon-Ross:
Exploiting dynamic phase distance mapping for phase-based tuning of embedded systems. ICCD 2013: 363-368 - 2012
- [c1]Tosiron Adegbija, Ann Gordon-Ross, Arslan Munir:
Dynamic phase-based tuning for embedded systems using phase distance mapping. ICCD 2012: 284-290
Informal and Other Publications
- 2024
- [i22]Ilkin Aliyev, Tosiron Adegbija:
PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine. CoRR abs/2402.06210 (2024) - [i21]Ilkin Aliyev, Tosiron Adegbija:
Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks. CoRR abs/2402.06211 (2024) - [i20]Yuchao Liao, Tosiron Adegbija, Roman Lysecky, Ravi Tandon:
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning. CoRR abs/2404.14754 (2024) - [i19]Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
A high-level synthesis approach for precisely-timed, energy-efficient embedded systems. CoRR abs/2404.14769 (2024) - [i18]Ping Chang, Tosiron Adegbija, Yuchao Liao, Claudio Talarico, Ao Li, Janet Roveda:
Deep Inverse Design for High-Level Synthesis. CoRR abs/2407.08797 (2024) - [i17]Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija:
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. CoRR abs/2407.19604 (2024) - [i16]Dhruv Gajaria, Tosiron Adegbija:
ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors. CoRR abs/2407.19612 (2024) - [i15]Dhruv Gajaria, Tosiron Adegbija, Kevin Antony Gomez:
CHIME: Energy-Efficient STT-RAM-based Concurrent Hierarchical In-Memory Processing. CoRR abs/2407.19627 (2024) - [i14]Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija:
STT-RAM-based Hierarchical In-Memory Computing. CoRR abs/2407.19637 (2024) - [i13]Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
Are LLMs Any Good for High-Level Synthesis? CoRR abs/2408.10428 (2024) - [i12]Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints. CoRR abs/2408.10431 (2024) - [i11]Ilkin Aliyev, Kama Svoboda, Tosiron Adegbija, Jean-Marc Fellous:
Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview. CoRR abs/2408.14437 (2024) - 2023
- [i10]Tosiron Adegbija:
jazznet: A Dataset of Fundamental Piano Patterns for Music Audio Machine Learning Research. CoRR abs/2302.08632 (2023) - [i9]Ilkin Aliyev, Kama Svoboda, Tosiron Adegbija:
Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators. CoRR abs/2310.16745 (2023) - 2020
- [i8]Kyle Kuan, Tosiron Adegbija:
A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. CoRR abs/2009.11442 (2020) - 2019
- [i7]Kyle Kuan, Tosiron Adegbija:
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. CoRR abs/1904.09363 (2019) - [i6]Kyle Kuan, Tosiron Adegbija:
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. CoRR abs/1905.07511 (2019) - [i5]Keeley Criswell, Tosiron Adegbija:
A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior. CoRR abs/1908.02238 (2019) - [i4]Kyle Kuan, Tosiron Adegbija:
Energy and Performance Analysis of STTRAM Caches for Mobile Applications. CoRR abs/1908.04744 (2019) - 2016
- [i3]Tosiron Adegbija, Ann Gordon-Ross:
Temperature-aware Dynamic Optimization of Embedded Systems. CoRR abs/1602.04414 (2016) - [i2]Tosiron Adegbija, Ann Gordon-Ross, Arslan Munir:
Phase distance mapping: a phase-based cache tuning methodology for embedded systems. CoRR abs/1602.04415 (2016) - [i1]Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, Ann Gordon-Ross:
Microprocessor Optimizations for the Internet of Things. CoRR abs/1603.02393 (2016)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 22:07 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
