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Dhruv Gajaria
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2020 – today
- 2024
- [j6]Alaba Yusuf
, Tosiron Adegbija
, Dhruv Gajaria
:
Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey. IEEE Access 12: 28036-28056 (2024) - [j5]Dhruv Gajaria
, Kevin Antony Gomez
, Tosiron Adegbija
:
STT-RAM-Based Hierarchical in-Memory Computing. IEEE Trans. Parallel Distributed Syst. 35(9): 1615-1629 (2024) - [i4]Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija:
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. CoRR abs/2407.19604 (2024) - [i3]Dhruv Gajaria, Tosiron Adegbija:
ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors. CoRR abs/2407.19612 (2024) - [i2]Dhruv Gajaria, Tosiron Adegbija, Kevin Antony Gomez:
CHIME: Energy-Efficient STT-RAM-based Concurrent Hierarchical In-Memory Processing. CoRR abs/2407.19627 (2024) - [i1]Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija:
STT-RAM-based Hierarchical In-Memory Computing. CoRR abs/2407.19637 (2024) - 2023
- [b1]Dhruv Gajaria:
STT-RAM-Based Domain-Specific Architectures for Resource-Constrained Systems. University of Arizona, Tucson, USA, 2023 - [j4]Serhan Gener, Parker Dattilo, Dhruv Gajaria, Alexander Fusco, Ali Akoglu
:
Gpu-based and streaming-enabled implementation of pre-processing flow towards enhancing optical character recognition accuracy and efficiency. Clust. Comput. 26(6): 3407-3419 (2023) - 2022
- [j3]Dhruv Gajaria
, Tosiron Adegbija:
Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads. Future Gener. Comput. Syst. 136: 231-240 (2022) - [j2]Dhruv Gajaria
, Tosiron Adegbija
:
Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing. J. Signal Process. Syst. 94(6): 559-577 (2022) - [c4]Serhan Gener
, Parker Dattilo, Dhruv Gajaria
, Alexander Fusco, Ali Akoglu
:
GPGPU-based High Throughput Image Pre-processing Towards Large-Scale Optical Character Recognition. AICCSA 2022: 1-7 - [c3]Dhruv Gajaria
, Kevin Antony Gomez, Tosiron Adegbija:
A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy. ICCD 2022: 685-692 - 2020
- [j1]Renato Cordeiro, Dhruv Gajaria
, Ankur Limaye
, Tosiron Adegbija
, Nima Karimian
, Fatemeh Tehranipoor
:
ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3373-3384 (2020)
2010 – 2019
- 2019
- [c2]Dhruv Gajaria
, Kyle Kuan, Tosiron Adegbija:
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. IGSC 2019: 1-7 - [c1]Dhruv Gajaria
, Tosiron Adegbija:
ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors. MEMSYS 2019: 439-450
Coauthor Index
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last updated on 2024-08-22 20:52 CEST by the dblp team
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