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ORCIDStergios Stergiou
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2020 – today
- 2020
[c13]Stergios Stergiou:
Scaling PageRank to 100 Billion Pages. WWW 2020: 2761-2767
2010 – 2019
- 2018
- [c12]Stergios Stergiou, Dipen Rughwani, Kostas Tsioutsiouliklis:
Shortcutting Label Propagation for Distributed Connected Components. WSDM 2018: 540-546 - 2017
- [c11]Stergios Stergiou, Zygimantas Straznickas, Rolina Wu, Kostas Tsioutsiouliklis:
Distributed Negative Sampling for Word Embeddings. AAAI 2017: 2569-2575 - 2015
- [c10]Stergios Stergiou, Kostas Tsioutsiouliklis:
Set Cover at Web Scale. KDD 2015: 1125-1133 - 2014
- [j5]Stergios Stergiou, Rajalakshmi Balakrishnan:
Streaming Updates for Heart Rate Variability Algorithms. IEEE Trans. Biomed. Eng. 61(7): 1931-1937 (2014) - 2013
- [c9]Stergios Stergiou, Jawahar Jain:
Optimizing BDDs for time-series dataset manipulation. DATE 2013: 1018-1021 - 2011
- [c8]Stergios Stergiou:
Implicit permutation enumeration networks and binary decision diagrams reordering. DAC 2011: 615-620 - 2010
- [c7]Stergios Stergiou, Jawahar Jain:
Dynamically resizable binary decision diagrams. ACM Great Lakes Symposium on VLSI 2010: 185-190
2000 – 2009
- 2008
- [c6]Stergios Stergiou, Jawahar Jain:
Optimizing routing tables on systems-on-chip with Content-Addressable Memories. SoC 2008: 1-6 - 2007
- [j4]Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini
, Giovanni De Micheli:
Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1297-1310 (2007) - 2006
- [b1]Stergios Stergiou:
Αλγόριθμοι βελτιστοποίησης λογικών παραστάσεων με πύλες ισοδυναμίας. National Technical University of Athens, Greece, 2006 - [c5]Stergios Stergiou, Jawahar Jain:
Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis. HLDVT 2006: 29-36 - 2005
- [j3]Dimitrios Voudouris, Stergios Stergiou, George K. Papakonstantinou:
Minimization of Reversible Wave Cascades. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 1015-1023 (2005) - [j2]Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli:
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. IEEE Trans. Parallel Distributed Syst. 16(2): 113-129 (2005) - [c4]Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli:
xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips. DATE 2005: 1188-1193 - 2004
- [j1]Stergios Stergiou, George K. Papakonstantinou:
Exact Minimization Of Esop Expressions With Less Than Eight Product Terms. J. Circuits Syst. Comput. 13(1): 1-15 (2004) - [c3]Stergios Stergiou, Konstantinos Daskalakis, George K. Papakonstantinou:
A fast and efficient heuristic ESOP minimization algorithm. ACM Great Lakes Symposium on VLSI 2004: 78-81 - 2001
- [c2]Stavros S. Cosmadakis, Kleoni Ioannidou, Stergios Stergiou:
View Serializable Updates of Concurrent Index Structures. DBPL 2001: 247-262 - [c1]George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos:
A Multi-Lingual Synthesis and Verification Environment. DSD 2001: 8-15
Coauthor Index
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