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Ting-Ting Y. Lin
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1990 – 1999
- 1997
- [j6]Zhiyu Tian, Ting-Ting Y. Lin, Shiyuan Yang, Shibai Tong:
The Faulty Behavior of Feedforward Neural Networks with Hard-limiting Activation Fuction. Neural Comput. 9(5): 1109-1126 (1997) - 1996
- [j5]John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid State Circuits 31(3): 437-447 (1996) - [c10]Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng:
Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming. DAC 1996: 274-279 - [c9]John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho:
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. DAC 1996: 395-400 - [c8]John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Simultaneous Routing and Buffer Insertion for High Performance Interconnect. Great Lakes Symposium on VLSI 1996: 148-153 - 1995
- [j4]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimization by iterative improvement: an experimental evaluation on two-way partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 145-153 (1995) - [j3]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Circuit clustering using a stochastic flow injection method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 154-162 (1995) - [c7]Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Performance driven multiple-source bus synthesis using buffer insertion. ASP-DAC 1995 - [c6]John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimal wire sizing and buffer insertion for low power and a generalized delay model. ICCAD 1995: 138-143 - [c5]Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimization of power dissipation and skew sensitivity in clock buffer synthesis. ISLPD 1995: 179-184 - 1994
- [j2]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A general purpose, multiple-way partitioning algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1480-1488 (1994) - [c4]Amiya Bhattacharya, Ramesh R. Rao, Ting-Ting Y. Lin:
Performability analysis of non-repairable multicomponent systems using order statistics. SPDP 1994: 646-653 - 1993
- [j1]Ting-Ting Y. Lin, Huoy-Yu Liou:
A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy. IEEE Des. Test Comput. 10(4): 38-51 (1993) - [c3]Amiya Bhattacharya, Ramesh R. Rao, Ting-Ting Y. Lin:
Delay Analysis in Synchronous Circuit-Switched Delta Networks. IPPS 1993: 666-670 - 1992
- [c2]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A probabilistic multicommodity-flow solution to circuit clustering problems. ICCAD 1992: 428-431 - 1991
- [c1]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A General Purpose Multiple Way Partitioning Algorithm. DAC 1991: 421-426
Coauthor Index
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