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ORCIDYasuto Kuroda
2010 – 2019
- 2016
[j9]Hideaki Furukawa, Hiroaki Harai, Yasuto Kuroda, Yuji Yano, Shoji Koyama:
Demonstration of 100 Gbps optical packet switching using header processor based on 48-bit longest prefix matching. Photonic Netw. Commun. 31(3): 483-492 (2016)- [c10]Masami Nawa, Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka:
Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure. CCNC 2016: 309-314 - 2015
- [c9]Hideaki Furukawa, Hiroaki Harai, Yasuto Kuroda, Shoji Koyama:
Demonstrating 100 Gbps optical packet switching using 16-bit longest prefix matching forwarding engine. ONDM 2015: 104-109 - 2014
- [c8]Hideaki Furukawa, Takaya Miyazawa, Hiroaki Harai, Yasuto Kuroda, Shoji Koyama, Shin'ichi Arakawa, Masayuki Murata
:
Development of onboard LPM-based header processing and reactive link selection for optical packet and circuit integrated networks. ICC 2014: 3277-3282 - 2013
- [j8]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue:
Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS. IEICE Trans. Commun. 96-B(7): 1819-1825 (2013) - [j7]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Kazunari Inoue, Ikuo Oka:
A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application. IEICE Trans. Electron. 96-C(8): 1076-1082 (2013) - [j6]Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai:
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. IEEE J. Solid State Circuits 48(11): 2671-2680 (2013) - [j5]Sou Koyano, Shingo Ata, Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Kazunari Inoue, Ikuo Oka:
A study on micro level traffic prediction for energy-aware routers. ACM SIGOPS Oper. Syst. Rev. 47(3): 26-33 (2013) - [c7]Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka:
2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving. CCNC 2013: 97-105 - 2012
- [j4]Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka:
FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine. IEICE Trans. Commun. 95-B(7): 2306-2314 (2012) - [c6]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue:
Deterministic High Density Packet-Buffer System for Low Cost Network Systems. AINA 2012: 951-956 - [c5]Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki:
A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application. CICC 2012: 1-4 - [c4]Yuji Yano, Hisashi Iwamoto, Yasuto Kuroda, Shiro Ohtani, Shingo Ata, Kazunari Inoue:
A slice structure using the management of network traffic prediction for green IT. HPSR 2012: 250-255 - 2010
- [c3]Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka:
Hardware implementation of fast forwarding engine using standard memory and dedicated circuit. ICECS 2010: 379-382
2000 – 2009
- 2008
- [j3]Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. 91-C(9): 1409-1418 (2008) - 2007
- [j2]Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. 90-D(1): 334-345 (2007) - [j1]Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. 90-D(8): 1312-1315 (2007) - [c2]Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS 2007: 525-528 - 2005
- [c1]Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) 2005: 5202-5205
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