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ORCIDYin Sun 0005
Person information
- affiliation: Nanyang Technological University, Singapore
Other persons with the same name
- Yin Sun — disambiguation page
- Yin Sun 0001
![[0000-0001-6811-984X]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-6811-984X")
— Auburn University, Department of Electrical and Computer Engineering, College of Engineering, AL, USA (and 2 more) - Yin Sun 0002 — Beijing University of Technology, Key Laboratory of Advanced Manufacturing Technology, China
- Yin Sun 0003 — Zhejiang Lab, Hangzhou, China (and 1 more)
- Yin Sun 0004 — Shell Global Solutions International BV, New Energies Research & Technology, Den Haag, Netherlands (and 1 more)
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2020 – today
- 2025
[c12]Junkai Zhao, Caoyang Yu, Jiwei Wang, Yin Sun, Tony Zhang, Tong Ge, Kwen-Siong Chong, Wei Shu, Joseph S. Chang:
An Improved AI-Based Micro-Single-Event-Latchup (Micro-SEL) and SEL Detection in a COTS System Against R/C/L-Induced (Power Management) Distortions. ICECS 2025: 1-4- [c11]Yin Sun, Junkai Zhao, Rouli Fang, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang:
Live Demonstration: AI-based System Latchup Detection and Protection for COTS Systems. ISCAS 2025: 1 - [c10]Junkai Zhao, Yin Sun, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang:
An Adaptive AI-based Approach to Detect and Protect COTS Systems against Micro-Single-Event-Latchups (μ-SELs) and SELs. ISCAS 2025: 1-5 - 2022
- [c9]Jinhen Lee, Victor Adrian, Joseph S. Chang, Yin Sun, Sun-Yang Tay:
An Integrated DC-DC Converter with Novel Asymmetrical Segmented Power-Stages for Sustained High Power-Efficiencies. ISCAS 2022: 3053-3057
2010 – 2019
- 2018
- [c8]Yin Sun, Victor Adrian, Tong Ge, Joseph S. Chang:
A Circuit for Reducing the Reverse Current in DCM DC-DC Converters. DSP 2018: 1-4 - [c7]Yin Sun, Victor Adrian, Joseph S. Chang:
Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters. ISCAS 2018: 1-4 - 2017
- [c6]Yin Sun, Victor Adrian, Joseph S. Chang:
A novel high-rate hybrid window ADC design for monolithic digitally-controlled DC-DC converters. ISCAS 2017: 1-4 - [c5]Cui Keer, Victor Adrian, Yin Sun, Bah-Hwee Gwee, Joseph S. Chang:
A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters. NEWCAS 2017: 165-168 - 2015
- [c4]Yin Sun, Victor Adrian, Joseph S. Chang:
Design of a variable-delay window ADC for switched-mode DC-DC converters. ISCAS 2015: 1642-1645 - 2014
- [c3]Victor Adrian, Yin Sun, Joseph Sylvester Chang:
Design of a 5 GS/s fully-digital digital-to-analog converter. ISCAS 2014: 1548-1551 - [c2]Tian-Shun Ng, Yin Sun, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang:
Design of an output stage for high switching frequency DC-DC converters. ISIC 2014: 488-491 - 2011
- [c1]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, Yin Sun, Kok-Leong Chang:
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation. ISCAS 2011: 1936-1939
Coauthor Index
aka: Joseph S. Chang
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