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2000 – 2009
- 2007
[c8]Kim T. Le, Dong Hyun Baik, Kewal K. Saluja:
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. VLSI Design 2007: 769-774- 2006
- [c7]Dong Hyun Baik, Kewal K. Saluja:
Test Cost Reduction Using Partitioned Grid Random Access Scan. VLSI Design 2006: 169-174 - 2005
- [j1]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
Yield-Driven, False-Path-Aware Clock Skew Scheduling. IEEE Des. Test Comput. 22(3): 214-222 (2005) - [c6]Dong Hyun Baik, Kewal K. Saluja:
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. Asian Test Symposium 2005: 272-277 - [c5]Dong Hyun Baik, Kewal K. Saluja:
Progressive random access scan: a simultaneous solution to test power, test data volume and test time. ITC 2005: 10 - [c4]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design 2005: 423-426 - 2004
- [c3]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ICCAD 2004: 611-618 - [c2]Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara:
Random Access Scan: A solution to test power, test data volume and test time. VLSI Design 2004: 883-888 - 2003
- [c1]Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja:
Exclusive Test and its Applications to Fault Diagnosis. VLSI Design 2003: 143-148
Coauthor Index
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