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2010 – 2019
- 2015
[j5]Te Huang, Ying-Wen Bai, Po-Yang Hsu:
Reducing the Standby Power Consumption of the S3 State for PCs. IEICE Trans. Electron. 98-C(10): 952-962 (2015)- 2014
- [j4]Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu:
Hybrid LUT and SOP Reconfigurable Architecture. J. Inf. Sci. Eng. 30(1): 65-84 (2014) - [j3]Po-Yang Hsu, Yi-Yu Liu:
Buffer Design and Assignment for Structured ASIC. J. Inf. Sci. Eng. 30(1): 107-124 (2014) - [j2]Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang:
Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 1031-1042 (2014) - [c5]Po-Yang Hsu, Pei-Lan Lin, TingTing Hwang:
Compaction-free compressed cache for high performance multi-core system. ICCAD 2014: 140-147 - 2013
- [j1]Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu:
Routability optimization for crossbar-switch structured ASIC design. ACM Trans. Design Autom. Electr. Syst. 18(3): 39:1-39:28 (2013) - [c4]Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang:
Stacking signal TSV for thermal dissipation in global routing for 3D IC. ASP-DAC 2013: 699-704 - [c3]Te Huang, Ying-Wen Bai, Po-Yang Hsu:
Reducing the standby power consumption of the S3 state for PCS. CCECE 2013: 1-6 - [c2]Po-Yang Hsu, TingTing Hwang:
Thread-criticality aware dynamic cache reconfiguration in multi-core system. ICCAD 2013: 413-420
2000 – 2009
- 2009
- [c1]Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu:
Buffer design and optimization for lut-based structured ASIC design styles. ACM Great Lakes Symposium on VLSI 2009: 377-380
Coauthor Index
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