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Richard Rouse
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2010 – 2019
- 2012
- [c5]Socrates D. Vamvakos, Bendik Kleveland, Dipak K. Sikdar, B. K. Ahuja, Haidang Lin, Jayaprakash Balachandran, Wignes Balakrishnan, Aldo Bottelli, Jawji Chen, Xiaole Chen, Jae Choi, Jeong Choi, Rajesh Chopra, Sanjay Dabral, Kalyan Dasari, Ronald B. David, Shaishav Desai, Claude R. Gauthier, Mahmudul Hassan, Kuo-Chiang Hsieh, Ramosan Canagasaby, Jeff Kumala, E. P. Kwon, Ben Lee, Ming Liu, Gurupada Mandal, Sundari Mitra, Byeong Cheol Na, Siddharth Panwar, Jay Patel, Chethan Rao, Vithal Rao, Richard Rouse, Ritesh Saraf, Subramanian Seshadri, Jae-K. Sim, Clement Szeto, Alvin Wang, Jason Yeung:
A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency. ESSCIRC 2012: 458-461 - [c4]Socrates D. Vamvakos, Claude R. Gauthier, Chethan Rao, Karthisha Ramoshan Canagasaby, Prashant Choudhary, Sanjay Dabral, Shaishav Desai, Mahmudul Hassan, Kuo-Chiang Hsieh, Bendik Kleveland, Gurupada Mandal, Richard Rouse, Ritesh Saraf, Alvin Wang, Jason Yeung, Khaldoon Abugharbieh
, Ying Cao:
A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications. MWSCAS 2012: 5-8
2000 – 2009
- 2008
- [c3]Nishath Verghese, Richard Rouse, Philippe Hurat:
Predictive models and CAD methodology for pattern dependent variability. ASP-DAC 2008: 213-218 - 2007
- [c2]Pei-Hua Wang, Brian Lee, Gus Han, Richard Rouse, Philippe Hurat, Nishath Verghese:
Addressing Parametric Impact of Systematic Pattern Variations in Digital IC Design. CICC 2007: 587-590 - [c1]Thierry Devoivre, Richard Rouse, Nishath Verghese, Philippe Hurat:
Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices. CICC 2007: 615-618
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