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ORCIDPey-Chang Kent Lin
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2010 – 2019
- 2015
[c10]Clayton B. McDonald, Hsinwei Chou, Vijay Durairaj, Pey-Chang Kent Lin:
Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States. ICCAD 2015: 802-807- 2013
- [c9]Pey-Chang Kent Lin, Sunil P. Khatri:
Noise-based algorithms for functional equivalence and tautology checking. ICCD 2013: 235-240 - 2012
- [c8]Pey-Chang Kent Lin, Sunil P. Khatri:
Application of logic synthesis to the understanding and cure of genetic diseases. DAC 2012: 734-740 - [c7]Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri:
Boolean satisfiability using noise based logic. DAC 2012: 1260-1261 - [c6]Pey-Chang Kent Lin, Sunil P. Khatri:
Determining gene function in boolean networks using boolean satisfiability. GENSiPS 2012: 176-179 - [c5]Subramanian Poothamkurissi Swaminathan, Pey-Chang Kent Lin, Sunil P. Khatri:
Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening. ICCD 2012: 153-158 - 2011
- [c4]Pey-Chang Kent Lin, Sunil P. Khatri:
Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG. GENSiPS 2011: 87-90 - [c3]Pey-Chang Kent Lin, Alex Ivanov, Bradley Johnson, Sunil P. Khatri:
A novel cryptographic key exchange scheme using resistors. ICCD 2011: 451-452 - [i1]Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri:
Boolean Satisfiability using Noise Based Logic. CoRR abs/1110.0550 (2011) - 2010
- [c2]Pey-Chang Kent Lin, Sunil P. Khatri:
Inference of gene predictor set using Boolean satisfiability. GENSiPS 2010: 1-4 - [c1]Pey-Chang Kent Lin, Sunil P. Khatri:
VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. ACM Great Lakes Symposium on VLSI 2010: 381-384
Coauthor Index
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