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ORCIDYasuaki Nishitani
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2020 – today
- 2024
[j13]Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani:
New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. IEICE Trans. Inf. Syst. 107(8): 940-948 (2024)- 2023
- [c8]Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani:
Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. ISMVL 2023: 153-157
2010 – 2019
- 2018
- [j12]Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani:
Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2231-2243 (2018) - 2016
- [c7]Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani:
New Two-Qubit Gate Library with Entanglement. ISMVL 2016: 235-240 - 2014
- [j11]Takashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani:
A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. IEICE Trans. Inf. Syst. 97-D(9): 2253-2261 (2014) - [j10]Kazuya Yamashita, Yasuaki Nishitani, Sadaki Hirose, Satoshi Okawa, Nobuyasu Osato:
The firing squad synchronization problem with sub-generals. Inf. Process. Lett. 114(1-2): 60-65 (2014) - 2011
- [c6]Takashi Hirayama, Yasuaki Nishitani, Seiji Kitamura:
A Testable Realization for Decimal Multipliers. ISMVL 2011: 248-253 - 2010
- [j9]Kazuya Yamashita, Mitsuru Sakai, Sadaki Hirose, Yasuaki Nishitani:
The Firing Squad Synchronization Problems for Number Patterns on a Seven-Segment Display and Segment Arrays. IEICE Trans. Inf. Syst. 93-D(12): 3276-3283 (2010)
2000 – 2009
- 2009
- [j8]Takashi Hirayama, Yasuaki Nishitani:
Exact Minimization of and-EXOR Expressions of Practical Benchmark Functions. J. Circuits Syst. Comput. 18(3): 465-486 (2009) - 2006
- [c5]Takashi Hirayama, Masatoshi Takahashi, Yasuaki Nishitani:
Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation. APCCAS 2006: 1480-1483 - [c4]Takashi Hirayama, Yasuaki Nishitani:
Efficient Search Methods for Obtaining Exact Minimum AND-EXOR Expressions. DELTA 2006: 137-142 - 2002
- [j7]Takashi Hirayama, Yasuaki Nishitani, Toru Sato:
A Faster Algorithm of Minimizing AND-EXOR Expressions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2708-2714 (2002) - [c3]Takashi Hirayama, Yasuaki Nishitani, Toru Sato:
A faster algorithm of minimizing AND-EXOR expressions. APCCAS (2) 2002: 293-298
1990 – 1999
- 1999
- [j6]Yoshihide Igarashi, Yasuaki Nishitani:
Speedup of the n-Process Mutual Exclusion Algorithm. Parallel Process. Lett. 9(4): 475-485 (1999) - [c2]Yoshihide Igarashi, Yasuaki Nishitani:
Speedup of Lockout-Free Mutual Exclusion Algorithms. ISPAN 1999: 172-177 - 1996
- [j5]Koji Obokata, Yasuaki Nishitani, Yoshihide Igarashi:
A Probably Optimal Embedding of Hyper-Rings in Hypercubes. Inf. Process. Lett. 58(3): 117-122 (1996) - [j4]Takashi Hirayama, Yasuaki Nishitani:
A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions. Syst. Comput. Jpn. 27(3): 18-25 (1996) - 1995
- [c1]Yukihiro Hamada, Aohan Mei, Yasuaki Nishitani, Yoshihide Igarashi:
Embeddings of Hyper-Rings in Hypercubes. ISAAC 1995: 312-321 - 1992
- [j3]Yasuaki Nishitani, Kensuke Shimizu, Masahiko Nagumo:
Graph representation of logic functions to design two-level MOS networks. Syst. Comput. Jpn. 23(1): 15-24 (1992)
1980 – 1989
- 1982
- [j2]T. Ito, Yasuaki Nishitani:
On Universality of Concurrent Expressions with Synchronization Primitives. Theor. Comput. Sci. 19: 105-115 (1982) - 1981
- [j1]Yasuaki Nishitani, Namio Honda:
The Firing Squad Synchronization Problem for Graphs. Theor. Comput. Sci. 14: 39-61 (1981)
Coauthor Index
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