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2010 – 2019
- 2012
[j9]Patrick Adde, Daniel Gomez Toro, Christophe Jégo:
Design of an Efficient Maximum Likelihood Soft Decoder for Systematic Short Block Codes. IEEE Trans. Signal Process. 60(7): 3914-3919 (2012)- [c13]Patrick Adde, Raphaël Le Bidan:
A low-complexity soft-decision decoding architecture for the binary extended Golay code. ICECS 2012: 705-708 - 2011
- [j8]Camille Leroux, Christophe Jégo, Patrick Adde, Deepak Gupta, Michel Jézéquel:
Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture. J. Signal Process. Syst. 64(1): 17-29 (2011) - 2010
- [j7]Sylvie Kerouédan, Makram Touzri, Patrick Adde, Samir Saoudi
:
A Turbo Decoder Included in a Multi-User Detector: A Solution to be Retained. Int. J. Commun. Netw. Syst. Sci. 3(10): 826-834 (2010) - [c12]Patrick Adde, Christophe Jégo, Raphaël Le Bidan, Jorge Ernesto Pérez Chamorro:
Design and implementation of a soft-decision decoder for Cortex codes. ICECS 2010: 663-666
2000 – 2009
- 2009
- [j6]Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel:
High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping. J. Signal Process. Syst. 57(3): 349-361 (2009) - 2008
- [j5]Raphaël Le Bidan, Camille Leroux, Christophe Jégo, Patrick Adde, Ramesh Pyndiah:
Reed-Solomon Turbo Product Codes for Optical Communications: From Code Optimization to Decoder Design. EURASIP J. Wirel. Commun. Netw. 2008 (2008) - [c11]Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel:
On the higher efficiency of parallel Reed-Solomon turbo-decoding. ICECS 2008: 1308-1311 - [c10]Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel, Deepak Gupta:
A highly parallel Turbo Product Code decoder without interleaving resource. SiPS 2008: 1-6 - 2007
- [j4]Christophe Jégo, Patrick Adde, Camille Leroux:
Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s. Ann. des Télécommunications 62(1-2): 214-239 (2007) - [c9]Raphaël Le Bidan, Ramesh Pyndiah, Patrick Adde:
Some Results on the Binary Minimum Distance of Reed-Solomon Codes and Block Turbo Codes. ICC 2007: 990-994 - [c8]Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel:
Towards Gb/s turbo decoding of product code onto an FPGA device. ISCAS 2007: 909-912 - 2006
- [j3]Javier Cuevas, Patrick Adde, Sylvie Kerouédan:
Information Theory Turbo decoding of product codes for Gigabit per second applications and beyond. Eur. Trans. Telecommun. 17(1): 45-55 (2006) - [c7]Erwan Piriou, Christophe Jégo, Patrick Adde, Raphaël Le Bidan, Michel Jézéquel:
Efficient architecture for Reed Solomon block turbo code. ISCAS 2006 - [c6]Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel:
A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes. ISVLSI 2006: 430-431 - [c5]Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel:
Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding. ReCoSoC 2006: 152-159 - 2002
- [c4]Javier Cuevas, Patrick Adde, Sylvie Kerouédan, Ramesh Pyndiah:
New architecture for high data rate turbo decoding of product codes. GLOBECOM 2002: 1363-1367 - 2001
- [j2]Sylvie Kerouédan, Patrick Adde, Ramesh Pyndiah:
How we implemented block turbo codes? Ann. des Télécommunications 56(7-8): 447-454 (2001) - [c3]Sylvie Kerouédan, Patrick Adde:
Block turbo codes: towards implementation. ICECS 2001: 1219-1222
1990 – 1999
- 1999
- [j1]Patrick Adde, Ramesh Pyndiah, Fabien Buda:
Design and performance of a product code turbo encoding-decoding prototype. Ann. des Télécommunications 54(3-4): 214-219 (1999) - 1996
- [c2]Pascale Ferry, Patrick Adde, Gérard Graton:
Turbo-decoder synchronisation procedure: application to the CAS5093 integrated circuit. ICECS 1996: 168-171 - [c1]Patrick Adde, Ramesh Pyndiah, Olivier Raoul:
Performance and complexity of block turbo decoder circuits. ICECS 1996: 172-175
Coauthor Index
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