Rung-Bin Lin

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Kuen-Wey Lin

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Publications

2018
[j15]
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Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin:
A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction. ACM Trans. Design Autom. Electr. Syst. 23(4): 45:1-45:26 (2018)
2017
[c44]
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  - conf/glvlsi/LinLLL17
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Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin:
A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points. ACM Great Lakes Symposium on VLSI 2017: 399-402
2016
[c41]
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  - conf/apccas/LinLL16
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Kuen-Wey Lin, Yih-Lang Li, Rung-Bin Lin:
Multiple-patterning lithography-aware routing for standard cell layout synthesis. APCCAS 2016: 534-537
2014
[c34]
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  - conf/glvlsi/LinLCL14
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Ta-Kai Lin, Kuen-Wey Lin, Chang-Hao Chiu, Rung-Bin Lin:
Logic block and design methodology for via-configurable structured ASIC using dual supply voltages. ACM Great Lakes Symposium on VLSI 2014: 111-116
2010
[c27]
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  - conf/date/ChenLTL10
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Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin:
Power gating design for standard-cell-like structured ASICs. DATE 2010: 514-519
[c26]
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  - conf/glvlsi/ChenPLLTS10
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Yu-Chen Chen, Hou-Yu Pang, Kuen-Wey Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su:
Via configurable three-input lookup-tables for structured ASICs. ACM Great Lakes Symposium on VLSI 2010: 49-54

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