Zhenyu Liu 0001

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Xiaocong Lian

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Publications

2019
[j30]
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Xiaocong Lian, Zhenyu Liu, Zhourui Song, Jiwu Dai, Wei Zhou, Xiangyang Ji:
High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1874-1885 (2019)
[c57]
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  - conf/globalsip/Zhang0ZDL0J19
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Heshan Zhang, Zhenyu Liu, Guanwen Zhang, Jiwu Dai, Xiaocong Lian, Wei Zhou, Xiangyang Ji:
A Block-Floating-Point Arithmetic Based FPGA Accelerator for Convolutional Neural Networks. GlobalSIP 2019: 1-5
2018
[j29]
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Xiaocong Lian, Zhenyu Liu, Wei Zhou, Zhemin Duan:
Parallel Content-Aware Adaptive Quantization-Oriented Lossy Frame Memory Recompression for HEVC. IEEE Trans. Circuits Syst. Video Technol. 28(4): 958-971 (2018)
2016
[j27]
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Xiaocong Lian, Zhenyu Liu, Wei Zhou, Zhemin Duan:
Lossless Frame Memory Compression Using Pixel-Grain Prediction and Dynamic Order Entropy Coding. IEEE Trans. Circuits Syst. Video Technol. 26(1): 223-235 (2016)
[c47]
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  - conf/apsipa/ZhouLZLZ16
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Xin Zhou, Xiaocong Lian, Wei Zhou, Zhenyu Liu, Xiu Zhang:
A low power lossy frame memory recompression algorithm. APSIPA 2016: 1-4
2015
[j24]
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  - journals/ejasp/ZhouZLLL15
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Wei Zhou, Xin Zhou, Xiaocong Lian, Zhenyu Liu, Xiaoxiang Liu:
An efficient interpolation filter VLSI architecture for HEVC standard. EURASIP J. Adv. Signal Process. 2015: 95 (2015)
[c41]
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Xiaocong Lian, Zhenyu Liu, Wei Zhou, Zhemin Duan:
Pixel-grain prediction and K-order UEG-rice entropy coding oriented lossless frame memory compression for motion estimation in HEVC. ICIP 2015: 1995-1999

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