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ORCIDTarik Graba
- > Home > Persons > Tarik Graba
Publications
- 2023
[c24]Guillaume Soudais, Tarik Graba, Yves Mathieu, Sébastien Bigo:
Jitter Compensation Mechanism for Dynamic Deterministic Networks. OFC 2023: 1-3- 2021
- [j7]Ville Yli-Mäyry
, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma:
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. 16: 1351-1364 (2021) - 2020
- [j6]Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69(4): 534-548 (2020) - 2018
- [c20]Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata:
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD 2018: 508-515 - 2017
- [j4]Xuan Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, Zakaria Najm, Shivam Bhasin:
Cryptographically Secure Shield for Security IPs Protection. IEEE Trans. Computers 66(2): 354-360 (2017) - 2016
- [i2]Sumanta Chaudhuri, Tarik Graba, Yves Mathieu:
Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. CoRR abs/1609.08681 (2016) - 2015
- [c18]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA. ICICDT 2015: 1-4 - 2014
- [c15]Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata:
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE 2014: 13 - [c14]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez:
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL 2014: 1-4 - [c13]Jean-Michel Cioranesco, Jean-Luc Danger, Tarik Graba, Sylvain Guilley, Yves Mathieu, David Naccache, Xuan Thuy Ngo:
Cryptographically secure shields. HOST 2014: 25-31 - 2013
- [c9]Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger, Yves Mathieu:
Design methodology of an ASIC TRNG based on an open-loop delay chain. NEWCAS 2013: 1-4 - 2009
- [c4]Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane:
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218 - 2008
- [c2]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu:
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. SSIRI 2008: 16-23
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