"High Throughput/Gate AES Hardware Architectures Based on Datapath Compression."

Rei Ueno et al. (2020)

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DOI: 10.1109/TC.2019.2957355

access: open

type: Journal Article

metadata version: 2023-07-27

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Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69(4): 534-548 (2020)

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