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ORCIDSonia López
- > Home > Persons > Sonia López
Publications
- 2011
[j2]Sonia López, Oscar Garnica
, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo:
A phase adaptive cache hierarchy for SMT processors. Microprocess. Microsystems 35(8): 683-694 (2011)- 2010
- [c10]Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo:
Adaptive Cache Memories for SMT Processors. DSD 2010: 331-338 - 2007
- [j1]Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar, Oscar Garnica, Sonia López:
Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders. IET Comput. Digit. Tech. 1(2): 113-119 (2007) - [c8]Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares:
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. PACT 2007: 416 - [c7]Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares:
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. HiPEAC 2007: 136-150 - 2006
- [c6]José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López:
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. DSD 2006: 423-432 - [c5]José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López:
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. Euro-Par 2006: 495-505 - [c4]Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López:
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. PATMOS 2006: 514-523 - 2004
- [c2]José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida:
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. PDP 2004: 112-119 - 2003
- [c1]Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida:
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. PATMOS 2003: 151-160
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