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Endri Bezati
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Publications
- 2022
- [c39]Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus:
Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks. PACT 2022: 398-411 - 2021
- [c38]Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus:
Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems. FPGA 2021: 226-227 - [c37]Süleyman Savas, Endri Bezati, Jörn W. Janneck:
Generating hardware and software for RISC-V cores generated with Rocket Chip generator. SoCC 2021: 89-94 - [i1]Endri Bezati, Mahyar Emami, Jörn W. Janneck, James R. Larus:
StreamBlocks: A compiler for heterogeneous dataflow computing (technical report). CoRR abs/2107.09333 (2021) - 2017
- [j7]Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck:
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4): 699-703 (2017) - 2016
- [j6]Massimo Canale, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck:
Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques - Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies. J. Signal Process. Syst. 84(3): 371-381 (2016) - [c23]Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck:
High-level system synthesis and optimization of dataflow programs for MPSoCs. ACSSC 2016: 417-421 - [c22]Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck:
Trace-based manycore partitioning of stream-processing applications. ACSSC 2016: 422-426 - [c16]Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck:
High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms. SAMOS 2016: 227-234 - 2014
- [c14]Jörn W. Janneck, Gustav Cedersjö, Endri Bezati, Simone Casale Brunet:
Dataflow machines. ACSSC 2014: 1848-1852 - [c13]Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Massimo Canale, Jörn W. Janneck:
Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. DASIP 2014: 1-6 - [c12]Simone Casale Brunet, M. Wiszniewska, Endri Bezati, Marco Mattavelli, Jörn W. Janneck, Massimo Canale:
TURNUS: An open-source design space exploration framework for dynamic stream programs. DASIP 2014: 1-2 - [c10]Massimo Canale, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck:
Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. SiPS 2014: 7-12 - 2013
- [j2]Simone Casale Brunet, Abdallah Elguindy, Endri Bezati, Richard Thavot, Ghislain Roquier, Marco Mattavelli, Jörn W. Janneck:
Methods to explore design space for MPEG RMC codec specifications. Signal Process. Image Commun. 28(10): 1278-1294 (2013) - [c9]Simone Casale Brunet, Endri Bezati, Claudio Alberti, Marco Mattavelli, Edoardo Amaldi, Jörn W. Janneck:
Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications. ACSSC 2013: 1796-1800 - [c8]Simone Casale Brunet, Endri Bezati, Claudio Alberti, Ghislain Roquier, Marco Mattavelli, Jörn W. Janneck, Jani Boutellier:
Design space exploration and implementation of RVC-CAL applications using the TURNUS framework. DASIP 2013: 341-342 - [c7]Endri Bezati, Marco Mattavelli, Jörn W. Janneck:
High-level synthesis of dataflow programs for signal processing systems. ISPA 2013: 750-754 - [c5]Simone Casale Brunet, Endri Bezati, Claudio Alberti, Marco Mattavelli, Edoardo Amaldi, Jörn W. Janneck:
Partitioning and optimization of high level stream applications for multi clock domain architectures. SiPS 2013: 177-182
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