Xueqing Li

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Taixin Li

> Home > Persons > Xueqing Li

Publications

2024
[j77]
- view
  authority control:
- export record
  dblp key:
  - journals/todaes/LiSZXNSWYKNYL24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/todaes/LiSZXNSWYKNYL24
Taixin Li, Boran Sun, Hongtao Zhong, Yixin Xu, Vijaykrishnan Narayanan, Liang Shi, Tianyi Wang, Yao Yu, Thomas Kämpfe, Kai Ni, Huazhong Yang, Xueqing Li:
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories. ACM Trans. Design Autom. Electr. Syst. 29(1): 3:1-3:18 (2024)
[c112]
- view
  - electronic edition @ ieee.org
  - no references & citations available
- export record
  dblp key:
  - conf/date/LiZWK0NYL24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/date/LiZWK0NYL24
Taixin Li, Hongtao Zhong, Juejian Wu, Thomas Kämpfe, Kai Ni, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li:
CafeHD: A Charge-Domain FeFET-Based Compute-in-Memory Hyperdimensional Encoder with Hypervector Merging. DATE 2024: 1-6
2023
[c100]
- view
  authority control:
- export record
  dblp key:
  - conf/iccad/WuLLXNLYL23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iccad/WuLLXNLYL23
Juejian Wu, Tianyu Liao, Taixin Li, Yixin Xu, Vijaykrishnan Narayanan, Yongpan Liu, Huazhong Yang, Xueqing Li:
Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices. ICCAD 2023: 1-9
[c97]
- view
  authority control:
- export record
  dblp key:
  - conf/isvlsi/LiZGNSYL23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/LiZGNSYL23
Taixin Li, Hongtao Zhong, Sumitha George, Vijaykrishnan Narayanan, Liang Shi, Huazhong Yang, Xueqing Li:
Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays. ISVLSI 2023: 1-6
[c96]
- view
  authority control:
- export record
  dblp key:
  - conf/isvlsi/ZhongZLLWXWYNLSYL23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/ZhongZLLWXWYNLSYL23
Hongtao Zhong, Yu Zhu, Longfei Luo, Taixin Li, Chen Wang, Yixin Xu, Tianyi Wang, Yao Yu, Vijaykrishnan Narayanan, Yongpan Liu, Liang Shi, Huazhong Yang, Xueqing Li:
Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks. ISVLSI 2023: 1-6

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.