Rakesh Malik

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Ashish Kumar 0001

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Publications

2017
[j2]
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Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik:
A 0.065-mm² 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB. IEEE J. Solid State Circuits 52(7): 1927-1939 (2017)
2016
[c13]
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  - conf/esscirc/KumarDSBCJTM16
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Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik:
A 0.065mm² 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB. ESSCIRC 2016: 165-168
2008
[c2]
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  - conf/cicc/SinghKDM08
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Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process. CICC 2008: 305-308
2007
[c1]
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Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process. CICC 2007: 189-192

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