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ORCIDRicardo Fernández Pascual
Publications
- 2024
[j20]Víctor Nicolás-Conesa
, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
On the interactions between ILP and TLP with hardware transactional memory. Microprocess. Microsystems 104: 104975 (2024)- 2022
- [j19]Marina Shimchenko, J. Rubén Titos Gil, Ricardo Fernández Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean:
Analysing software prefetching opportunities in hardware transactional memory. J. Supercomput. 78(1): 919-944 (2022) - [j18]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 33(1): 1-13 (2022) - [c16]Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. PDP 2022: 157-164 - 2020
- [j17]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. J. Parallel Distributed Comput. 145: 111-123 (2020) - [j16]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 31(6): 1301-1315 (2020) - 2019
- [j15]J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio:
Way Combination for an Adaptive and Scalable Coherence Directory. IEEE Trans. Parallel Distributed Syst. 30(11): 2608-2623 (2019) - 2017
- [j14]Juan M. Cebrian, Ricardo Fernández Pascual, Alexandra Jimborean, Manuel E. Acacio, Alberto Ros:
A dedicated private-shared cache design for scalable multiprocessors. Concurr. Comput. Pract. Exp. 29(2) (2017) - [j13]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
To be silent or not: on the impact of evictions of clean data in cache-coherent multicores. J. Supercomput. 73(10): 4428-4443 (2017) - [c15]J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Way-combining directory: an adaptive and scalable low-cost coherence directory. ICS 2017: 20:1-20:10 - 2016
- [j10]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study. J. Supercomput. 72(2): 612-638 (2016) - [c14]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence. ARCS 2016: 100-112 - 2015
- [c13]Juan M. Cebrian, Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio:
Early Experiences with Separate Caches for Private and Shared Data. e-Science 2015: 572-579 - 2014
- [c12]Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs. Euro-Par Workshops (2) 2014: 254-265 - 2012
- [j6]Alberto Ros, Blas Cuesta Saez, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato:
Extending Magny-Cours Cache Coherence. IEEE Trans. Computers 61(5): 593-606 (2012) - [c11]Manuel E. Acacio, Javier Cuenca, Lorenzo Fernández Maimó, Ricardo Fernández Pascual, Joaquín Cervera, Domingo Giménez, M. Carmen Garrido, Juan A. Sánchez-Laguna, José Guillén, Juan Alejandro Palomino Benito, María-Eugenia Requena:
An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain. IPDPS Workshops 2012: 1289-1294 - [c9]Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio:
Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. SBAC-PAD 2012: 43-50 - 2010
- [j5]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level. IEEE Trans. Parallel Distributed Syst. 21(8): 1117-1131 (2010) - [c7]Alberto Ros, Blas Cuesta, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato:
EMC2: Extending Magny-Cours coherence for large-scale servers. HiPC 2010: 1-10 - 2008
- [j4]Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio, José M. García:
Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. J. Parallel Distributed Comput. 68(11): 1413-1424 (2008) - [j3]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures. IEEE Trans. Parallel Distributed Syst. 19(8): 1044-1056 (2008) - [c5]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
A fault-tolerant directory-based cache coherence protocol for CMP architectures. DSN 2008: 267-276 - [c4]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. HiPC 2008: 555-568 - 2007
- [j2]Gregorio Bernabé, Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José González:
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. Parallel Comput. 33(1): 54-72 (2007) - [c2]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. HPCA 2007: 157-168 - 2005
- [c1]Ricardo Fernández Pascual, José M. García, Gregorio Bernabé, Manuel E. Acacio:
Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures. PDP 2005: 76-83
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