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Ai-Jia Chuang

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2020 – today

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2021
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Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang:
A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 883-894 (2021)

2010 – 2019

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2012
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Ai-Jia Chuang, Yu Lee, Ching-Yuan Yang:
A chip-to-chip clock-deskewing circuit for 3-D ICs. ISCAS 2012: 1652-1655

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