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ORCIDBibTeX records: Avinoam Kolodny
@article{DBLP:journals/jsac/ZahaviSRKK19,
author = {Eitan Zahavi and
Alexander Shpiner and
Ori Rottenstreich and
Avinoam Kolodny and
Isaac Keslassy},
title = {Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared
Cloud},
journal = {{IEEE} J. Sel. Areas Commun.},
volume = {37},
number = {5},
pages = {1072--1084},
year = {2019},
url = {https://doi.org/10.1109/JSAC.2019.2906747},
doi = {10.1109/JSAC.2019.2906747},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsac/ZahaviSRKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/MoradSEKW17,
author = {Tomer Y. Morad and
Gil Shomron and
Mattan Erez and
Avinoam Kolodny and
Uri C. Weiser},
title = {Optimizing Read-Once Data Flow in Big-Data Applications},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {16},
number = {1},
pages = {68--71},
year = {2017},
url = {https://doi.org/10.1109/LCA.2016.2520927},
doi = {10.1109/LCA.2016.2520927},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/MoradSEKW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jpdc/MoradSKKW16,
author = {Tomer Y. Morad and
Noam Shalev and
Idit Keidar and
Avinoam Kolodny and
Uri C. Weiser},
title = {{EFS:} Energy-Friendly Scheduler for memory bandwidth constrained
systems},
journal = {J. Parallel Distributed Comput.},
volume = {95},
pages = {3--14},
year = {2016},
url = {https://doi.org/10.1016/j.jpdc.2016.03.007},
doi = {10.1016/J.JPDC.2016.03.007},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jpdc/MoradSKKW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/ManevichCK16,
author = {Ran Manevich and
Israel Cidon and
Avinoam Kolodny},
title = {Design and dynamic management of hierarchical NoCs},
journal = {Microprocess. Microsystems},
volume = {40},
pages = {154--166},
year = {2016},
url = {https://doi.org/10.1016/j.micpro.2015.09.004},
doi = {10.1016/J.MICPRO.2015.09.004},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/ManevichCK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ancs/ZahaviSRKK16,
author = {Eitan Zahavi and
Alexander Shpiner and
Ori Rottenstreich and
Avinoam Kolodny and
Isaac Keslassy},
editor = {Patrick Crowley and
Luigi Rizzo and
Laurent Mathy},
title = {Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared
Cloud},
booktitle = {Proceedings of the 2016 Symposium on Architectures for Networking
and Communications Systems, {ANCS} 2016, Santa Clara, CA, USA, March
17-18, 2016},
pages = {87--98},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2881025.2881028},
doi = {10.1145/2881025.2881028},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ancs/ZahaviSRKK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MoiseevWK15,
author = {Konstantin Moiseev and
Shmuel Wimer and
Avinoam Kolodny},
title = {Timing-constrained power minimization in {VLSI} circuits by simultaneous
multilayer wire spacing},
journal = {Integr.},
volume = {48},
pages = {116--128},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.03.002},
doi = {10.1016/J.VLSI.2014.03.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MoiseevWK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Ben-ItzhakCK15,
author = {Yaniv Ben{-}Itzhak and
Israel Cidon and
Avinoam Kolodny},
title = {Average latency and link utilization analysis of heterogeneous wormhole
NoCs},
journal = {Integr.},
volume = {51},
pages = {92--106},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2015.07.002},
doi = {10.1016/J.VLSI.2015.07.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Ben-ItzhakCK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KvatinskyRFK15,
author = {Shahar Kvatinsky and
Misbah Ramadan and
Eby G. Friedman and
Avinoam Kolodny},
title = {{VTEAM:} {A} General Model for Voltage-Controlled Memristors},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {62-II},
number = {8},
pages = {786--790},
year = {2015},
url = {https://doi.org/10.1109/TCSII.2015.2433536},
doi = {10.1109/TCSII.2015.2433536},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/KvatinskyRFK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tnn/SoudryCGKK15,
author = {Daniel Soudry and
Dotan Di Castro and
Asaf Gal and
Avinoam Kolodny and
Shahar Kvatinsky},
title = {Memristor-Based Multilayer Neural Networks With Online Gradient Descent
Training},
journal = {{IEEE} Trans. Neural Networks Learn. Syst.},
volume = {26},
number = {10},
pages = {2408--2421},
year = {2015},
url = {https://doi.org/10.1109/TNNLS.2014.2383395},
doi = {10.1109/TNNLS.2014.2383395},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tnn/SoudryCGKK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/Ben-ItzhakCKSS15,
author = {Yaniv Ben{-}Itzhak and
Israel Cidon and
Avinoam Kolodny and
Michael Shabun and
Nir Shmuel},
title = {Heterogeneous NoC Router Architecture},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {26},
number = {9},
pages = {2479--2492},
year = {2015},
url = {https://doi.org/10.1109/TPDS.2014.2351816},
doi = {10.1109/TPDS.2014.2351816},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/Ben-ItzhakCKSS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PatelKFK15,
author = {Ravi Patel and
Shahar Kvatinsky and
Eby G. Friedman and
Avinoam Kolodny},
title = {Multistate Register Based on Resistive {RAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {9},
pages = {1750--1759},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2347926},
doi = {10.1109/TVLSI.2014.2347926},
timestamp = {Mon, 07 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PatelKFK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/ZahaviSRKK15,
author = {Eitan Zahavi and
Alexander Shpiner and
Ori Rottenstreich and
Avinoam Kolodny and
Isaac Keslassy},
title = {Links as a Service (LaaS): Feeling Alone in the Shared Cloud},
journal = {CoRR},
volume = {abs/1509.07395},
year = {2015},
url = {http://arxiv.org/abs/1509.07395},
eprinttype = {arXiv},
eprint = {1509.07395},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/ZahaviSRKK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/KvatinskyNEFKW14,
author = {Shahar Kvatinsky and
Yuval H. Nacson and
Yoav Etsion and
Eby G. Friedman and
Avinoam Kolodny and
Uri C. Weiser},
title = {Memristor-Based Multithreading},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {13},
number = {1},
pages = {41--44},
year = {2014},
url = {https://doi.org/10.1109/L-CA.2013.3},
doi = {10.1109/L-CA.2013.3},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/KvatinskyNEFKW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsac/ZahaviKK14,
author = {Eitan Zahavi and
Isaac Keslassy and
Avinoam Kolodny},
title = {Distributed Adaptive Routing Convergence to Non-Blocking {DCN} Routing
Assignments},
journal = {{IEEE} J. Sel. Areas Commun.},
volume = {32},
number = {1},
pages = {88--101},
year = {2014},
url = {https://doi.org/10.1109/JSAC.2014.140109},
doi = {10.1109/JSAC.2014.140109},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsac/ZahaviKK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/ManevichPCK14,
author = {Ran Manevich and
Leon Polishuk and
Israel Cidon and
Avinoam Kolodny},
title = {Designing single-cycle long links in hierarchical NoCs},
journal = {Microprocess. Microsystems},
volume = {38},
number = {8},
pages = {814--825},
year = {2014},
url = {https://doi.org/10.1016/j.micpro.2014.05.005},
doi = {10.1016/J.MICPRO.2014.05.005},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/ManevichPCK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/LevyBCFKYK14,
author = {Yifat Levy and
Jehoshua Bruck and
Yuval Cassuto and
Eby G. Friedman and
Avinoam Kolodny and
Eitan Yaakobi and
Shahar Kvatinsky},
title = {Logic operations in memory using a memristive Akers array},
journal = {Microelectron. J.},
volume = {45},
number = {11},
pages = {1429--1437},
year = {2014},
url = {https://doi.org/10.1016/j.mejo.2014.06.006},
doi = {10.1016/J.MEJO.2014.06.006},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/LevyBCFKYK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KvatinskyBLSWFKW14,
author = {Shahar Kvatinsky and
Dmitry Belousov and
Slavik Liman and
Guy Satat and
Nimrod Wald and
Eby G. Friedman and
Avinoam Kolodny and
Uri C. Weiser},
title = {{MAGIC} - Memristor-Aided Logic},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {61-II},
number = {11},
pages = {895--899},
year = {2014},
url = {https://doi.org/10.1109/TCSII.2014.2357292},
doi = {10.1109/TCSII.2014.2357292},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/KvatinskyBLSWFKW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KvatinskySWFKW14,
author = {Shahar Kvatinsky and
Guy Satat and
Nimrod Wald and
Eby G. Friedman and
Avinoam Kolodny and
Uri C. Weiser},
title = {Memristor-Based Material Implication {(IMPLY)} Logic: Design Principles
and Methodologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {10},
pages = {2054--2066},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2282132},
doi = {10.1109/TVLSI.2013.2282132},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KvatinskySWFKW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hoti/ZahaviKK14,
author = {Eitan Zahavi and
Isaac Keslassy and
Avinoam Kolodny},
title = {Quasi Fat Trees for {HPC} Clouds and Their Fault-Resilient Closed-Form
Routing},
booktitle = {22nd {IEEE} Annual Symposium on High-Performance Interconnects, {HOTI}
2014, Mountain View, CA, USA, August 26-28, 2014},
pages = {41--48},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/HOTI.2014.19},
doi = {10.1109/HOTI.2014.19},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hoti/ZahaviKK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AbdelhadiGKF13,
author = {Ameer Abdelhadi and
Ran Ginosar and
Avinoam Kolodny and
Eby G. Friedman},
title = {Timing-driven variation-aware synthesis of hybrid mesh/tree clock
distribution networks},
journal = {Integr.},
volume = {46},
number = {4},
pages = {382--391},
year = {2013},
url = {https://doi.org/10.1016/j.vlsi.2012.12.001},
doi = {10.1016/J.VLSI.2012.12.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AbdelhadiGKF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KvatinskyFKW13,
author = {Shahar Kvatinsky and
Eby G. Friedman and
Avinoam Kolodny and
Uri C. Weiser},
title = {{TEAM:} ThrEshold Adaptive Memristor Model},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {60-I},
number = {1},
pages = {211--221},
year = {2013},
url = {https://doi.org/10.1109/TCSI.2012.2215714},
doi = {10.1109/TCSI.2012.2215714},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/KvatinskyFKW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/ZahaviCK13,
author = {Eitan Zahavi and
Israel Cidon and
Avinoam Kolodny},
title = {Gana: {A} novel low-cost conflict-free NoC architecture},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {12},
number = {4},
pages = {109:1--109:20},
year = {2013},
url = {https://doi.org/10.1145/2485984.2485997},
doi = {10.1145/2485984.2485997},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/ZahaviCK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/ManevichPCK13,
author = {Ran Manevich and
Leon Polishuk and
Israel Cidon and
Avinoam Kolodny},
title = {Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip},
booktitle = {2013 Euromicro Conference on Digital System Design, {DSD} 2013, Los
Alamitos, CA, USA, September 4-6, 2013},
pages = {769--776},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/DSD.2013.88},
doi = {10.1109/DSD.2013.88},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/ManevichPCK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/ManevichCK13,
author = {Ran Manevich and
Israel Cidon and
Avinoam Kolodny},
title = {Dynamic traffic distribution among hierarchy levels in hierarchical
Networks-on-Chip (NoCs)},
booktitle = {2013 Seventh {IEEE/ACM} International Symposium on Networks-on-Chip
(NoCS), Tempe, AZ, USA, April 21-24, 2013},
pages = {1--8},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/NoCS.2013.6558412},
doi = {10.1109/NOCS.2013.6558412},
timestamp = {Wed, 16 Oct 2019 14:14:48 +0200},
biburl = {https://dblp.org/rec/conf/nocs/ManevichCK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/RehanaTMK13,
author = {Shani Rehana and
Or Turgeman and
Ran Manevich and
Avinoam Kolodny},
editor = {Norbert Schuhmann and
Kaijian Shi and
Nagi Naganathan},
title = {ViLoCoN - An ultra-lightweight lossless {VLSI} video codec},
booktitle = {2013 {IEEE} International {SOC} Conference, Erlangen, Germany, September
4-6, 2013},
pages = {172--177},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/SOCC.2013.6749683},
doi = {10.1109/SOCC.2013.6749683},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/RehanaTMK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jco/MoiseevKW12,
author = {Konstantin Moiseev and
Avinoam Kolodny and
Shmuel Wimer},
title = {The complexity of {VLSI} power-delay optimization by interconnect
resizing},
journal = {J. Comb. Optim.},
volume = {23},
number = {2},
pages = {292--300},
year = {2012},
url = {https://doi.org/10.1007/s10878-010-9355-1},
doi = {10.1007/S10878-010-9355-1},
timestamp = {Thu, 18 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jco/MoiseevKW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcp/MoradKW12,
author = {Tomer Y. Morad and
Avinoam Kolodny and
Uri C. Weiser},
title = {Task Scheduling Based On Thread Essence and Resource Limitations},
journal = {J. Comput.},
volume = {7},
number = {1},
pages = {53--64},
year = {2012},
url = {http://www.jcomputers.us/index.php?m=content\&\#38;c=index\&\#38;a=show\&\#38;catid=127\&\#38;id=1820},
doi = {10.4304/JCP.7.1.53-64},
timestamp = {Thu, 25 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcp/MoradKW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/VishnyakovFK12,
author = {Victoria Vishnyakov and
Eby G. Friedman and
Avinoam Kolodny},
title = {Multi-aggressor capacitive and inductive coupling noise modeling and
mitigation},
journal = {Microelectron. J.},
volume = {43},
number = {4},
pages = {235--243},
year = {2012},
url = {https://doi.org/10.1016/j.mejo.2011.12.007},
doi = {10.1016/J.MEJO.2011.12.007},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/VishnyakovFK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/MalitsBKM12,
author = {Roman Malits and
Evgeny Bolotin and
Avinoam Kolodny and
Avi Mendelson},
title = {Exploring the limits of {GPGPU} scheduling in control flow bound applications},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {29:1--29:22},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086708},
doi = {10.1145/2086696.2086708},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/MalitsBKM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ancs/ZahaviKK12,
author = {Eitan Zahavi and
Isaac Keslassy and
Avinoam Kolodny},
editor = {Tilman Wolf and
Andrew W. Moore and
Viktor K. Prasanna},
title = {Distributed adaptive routing for big-data applications running on
data center networks},
booktitle = {Symposium on Architecture for Networking and Communications Systems,
{ANCS} '12, Austin, TX, {USA} - October 29 - 30, 2012},
pages = {99--110},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2396556.2396578},
doi = {10.1145/2396556.2396578},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ancs/ZahaviKK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/VaisbandFGK12,
author = {Inna Vaisband and
Eby G. Friedman and
Ran Ginosar and
Avinoam Kolodny},
title = {Energy metrics for power efficient crosslink and mesh topologies},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {1656--1659},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6271575},
doi = {10.1109/ISCAS.2012.6271575},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/VaisbandFGK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/Ben-ItzhakZCK12,
author = {Yaniv Ben{-}Itzhak and
Eitan Zahavi and
Israel Cidon and
Avinoam Kolodny},
title = {{HNOCS:} Modular open-source simulator for Heterogeneous NoCs},
booktitle = {2012 International Conference on Embedded Computer Systems: Architectures,
Modeling, and Simulation, {SAMOS} XII, Samos, Greece, July 16-19,
2012},
pages = {51--57},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/SAMOS.2012.6404157},
doi = {10.1109/SAMOS.2012.6404157},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/samos/Ben-ItzhakZCK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Ben-ItzhakCK12,
author = {Yaniv Ben{-}Itzhak and
Israel Cidon and
Avinoam Kolodny},
title = {Optimizing heterogeneous NoC design},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {32--39},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347670},
doi = {10.1145/2347655.2347670},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Ben-ItzhakCK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ManevichCK12,
author = {Ran Manevich and
Israel Cidon and
Avinoam Kolodny},
title = {Handling global traffic in future {CMP} NoCs},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {40--47},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347671},
doi = {10.1145/2347655.2347671},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ManevichCK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jpdc/KrimerKKWE11,
author = {Evgeni Krimer and
Isaac Keslassy and
Avinoam Kolodny and
Isask'har Walter and
Mattan Erez},
title = {Static timing analysis for modeling QoS in networks-on-chip},
journal = {J. Parallel Distributed Comput.},
volume = {71},
number = {5},
pages = {687--699},
year = {2011},
url = {https://doi.org/10.1016/j.jpdc.2010.10.003},
doi = {10.1016/J.JPDC.2010.10.003},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jpdc/KrimerKKWE11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/AizikK11,
author = {Yoni Aizik and
Avinoam Kolodny},
title = {Finding the Energy Efficient Curve: Gate Sizing for Minimum Power
under Delay Constraints},
journal = {{VLSI} Design},
volume = {2011},
pages = {845957:1--845957:13},
year = {2011},
url = {https://doi.org/10.1155/2011/845957},
doi = {10.1155/2011/845957},
timestamp = {Sat, 24 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/AizikK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/ManevichCKWW11,
author = {Ran Manevich and
Israel Cidon and
Avinoam Kolodny and
Isask'har Walter and
Shmuel Wimer},
title = {A Cost Effective Centralized Adaptive Routing for Networks-on-Chip},
booktitle = {14th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2011, August 31 - September 2, 2011, Oulu,
Finland},
pages = {39--46},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/DSD.2011.10},
doi = {10.1109/DSD.2011.10},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/ManevichCKWW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/KvatinskyKWF11,
author = {Shahar Kvatinsky and
Avinoam Kolodny and
Uri C. Weiser and
Eby G. Friedman},
title = {Memristor-based {IMPLY} logic design procedure},
booktitle = {{IEEE} 29th International Conference on Computer Design, {ICCD} 2011,
Amherst, MA, USA, October 9-12, 2011},
pages = {142--147},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCD.2011.6081389},
doi = {10.1109/ICCD.2011.6081389},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/KvatinskyKWF11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/BeerGPDK11,
author = {Salomon Beer and
Ran Ginosar and
Michael Priel and
Rostislav (Reuven) Dobkin and
Avinoam Kolodny},
title = {An on-chip metastability measurement circuit to characterize synchronization
behavior in 65nm},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2011), May
15-19 2011, Rio de Janeiro, Brazil},
pages = {2593--2596},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCAS.2011.5938135},
doi = {10.1109/ISCAS.2011.5938135},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/BeerGPDK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/Ben-ItzhakCK11,
author = {Yaniv Ben{-}Itzhak and
Israel Cidon and
Avinoam Kolodny},
editor = {Radu Marculescu and
Michael Kishinevsky and
Ran Ginosar and
Karam S. Chatha},
title = {Delay analysis of wormhole based heterogeneous NoC},
booktitle = {{NOCS} 2011, Fifth {ACM/IEEE} International Symposium on Networks-on-Chip,
Pittsburgh, Pennsylvania, USA, May 1-4, 2011},
pages = {161--168},
publisher = {{ACM/IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1145/1999946.1999972},
doi = {10.1145/1999946.1999972},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/Ben-ItzhakCK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/Ben-ItzhakZCK11,
author = {Yaniv Ben{-}Itzhak and
Eitan Zahavi and
Israel Cidon and
Avinoam Kolodny},
editor = {Radu Marculescu and
Michael Kishinevsky and
Ran Ginosar and
Karam S. Chatha},
title = {NoCs simulation framework for OMNeT++},
booktitle = {{NOCS} 2011, Fifth {ACM/IEEE} International Symposium on Networks-on-Chip,
Pittsburgh, Pennsylvania, USA, May 1-4, 2011},
pages = {265--266},
publisher = {{ACM/IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1145/1999946.1999993},
doi = {10.1145/1999946.1999993},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/Ben-ItzhakZCK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/11/BerahaWCK11,
author = {Rudy Beraha and
Isask'har Walter and
Israel Cidon and
Avinoam Kolodny},
editor = {Cristina Silvano and
Marcello Lajolo and
Gianluca Palermo},
title = {Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: {A}
Case Study},
booktitle = {Low Power Networks-on-Chip},
pages = {175--195},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-1-4419-6911-8\_7},
doi = {10.1007/978-1-4419-6911-8\_7},
timestamp = {Fri, 02 Nov 2018 09:27:05 +0100},
biburl = {https://dblp.org/rec/books/sp/11/BerahaWCK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/ManevichCKW10,
author = {Ran Manevich and
Israel Cidon and
Avinoam Kolodny and
Isask'har Walter},
title = {Centralized Adaptive Routing for NoCs},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {9},
number = {2},
pages = {57--60},
year = {2010},
url = {https://doi.org/10.1109/L-CA.2010.17},
doi = {10.1109/L-CA.2010.17},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/ManevichCKW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MoiseevKW10,
author = {Konstantin Moiseev and
Avinoam Kolodny and
Shmuel Wimer},
title = {Interconnect Bundle Sizing Under Discrete Design Rules},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1650--1654},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2051633},
doi = {10.1109/TCAD.2010.2051633},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MoiseevKW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MorgenshteinFGK10,
author = {Arkadiy Morgenshtein and
Eby G. Friedman and
Ran Ginosar and
Avinoam Kolodny},
title = {Unified Logical Effort - {A} Method for Delay Evaluation and Minimization
in Logic Paths With {RC} Interconnect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {5},
pages = {689--696},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2014239},
doi = {10.1109/TVLSI.2009.2014239},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MorgenshteinFGK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DobkinMKG10,
author = {Rostislav (Reuven) Dobkin and
Michael Moyal and
Avinoam Kolodny and
Ran Ginosar},
title = {Asynchronous Current Mode Serial Communication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {7},
pages = {1107--1117},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2020859},
doi = {10.1109/TVLSI.2009.2020859},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DobkinMKG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MorgenshteinFGK10a,
author = {Arkadiy Morgenshtein and
Eby G. Friedman and
Ran Ginosar and
Avinoam Kolodny},
title = {Corrections to "Unified Logical Effort - {A} Method for Delay
Evaluation and Minimization in Logic Paths With {RC} Interconnect"
[May 10 689-696]},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {8},
pages = {1262},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2010.2052421},
doi = {10.1109/TVLSI.2010.2052421},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MorgenshteinFGK10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/BeerGPDK10,
author = {Salomon Beer and
Ran Ginosar and
Michael Priel and
Rostislav (Reuven) Dobkin and
Avinoam Kolodny},
title = {The Devolution of Synchronizers},
booktitle = {16th {IEEE} International Symposium on Asynchronous Circuits and Systems,
{ASYNC} 2010, Grenoble, France, 3-6 May 2010},
pages = {94--103},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ASYNC.2010.22},
doi = {10.1109/ASYNC.2010.22},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/BeerGPDK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BerahaWCK10,
author = {Rudy Beraha and
Isask'har Walter and
Israel Cidon and
Avinoam Kolodny},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {Leveraging application-level requirements in the design of a NoC for
a 4G SoC - a case study},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1408--1413},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457033},
doi = {10.1109/DATE.2010.5457033},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/BerahaWCK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AbdelhadiGKF10,
author = {Ameer Abdelhadi and
Ran Ginosar and
Avinoam Kolodny and
Eby G. Friedman},
editor = {R. Iris Bahar and
Fabrizio Lombardi and
David Atienza and
Erik Brunvand},
title = {Timing-driven variation-aware nonuniform clock mesh synthesis},
booktitle = {Proceedings of the 20th {ACM} Great Lakes Symposium on {VLSI} 2009,
Providence, Rhode Island, USA, May 16-18 2010},
pages = {15--20},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1785481.1785487},
doi = {10.1145/1785481.1785487},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/AbdelhadiGKF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Ben-ItzhakCK10,
author = {Yaniv Ben{-}Itzhak and
Israel Cidon and
Avinoam Kolodny},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Performance and Power Aware {CMP} Thread Allocation Modeling},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {232--246},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_18},
doi = {10.1007/978-3-642-11515-8\_18},
timestamp = {Tue, 14 May 2019 10:00:51 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Ben-ItzhakCK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GuzIKKMW10,
author = {Zvika Guz and
Oved Itzhak and
Idit Keidar and
Avinoam Kolodny and
Avi Mendelson and
Uri C. Weiser},
title = {Threads vs. caches: Modeling the behavior of parallel workloads},
booktitle = {28th International Conference on Computer Design, {ICCD} 2010, 3-6
October 2010, Amsterdam, The Netherlands, Proceedings},
pages = {274--281},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ICCD.2010.5647747},
doi = {10.1109/ICCD.2010.5647747},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/GuzIKKMW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SizikovKFZ10,
author = {Gregory Sizikov and
Avinoam Kolodny and
Eby G. Friedman and
Michael Zelikson},
title = {Efficiency optimization of integrated {DC-DC} buck converters},
booktitle = {17th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2010, Athens, Greece, 12-15 December, 2010},
pages = {1208--1211},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICECS.2010.5724735},
doi = {10.1109/ICECS.2010.5724735},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/SizikovKFZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/MoiseevKW10,
author = {Konstantin Moiseev and
Avinoam Kolodny and
Shmuel Wimer},
editor = {Prashant Saxena and
Yao{-}Wen Chang},
title = {Interconnect power and delay optimization by dynamic programming in
gridded design rules},
booktitle = {Proceedings of the 2010 International Symposium on Physical Design,
{ISPD} 2010, San Francisco, California, USA, March 14-17, 2010},
pages = {153--160},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1735023.1735061},
doi = {10.1145/1735023.1735061},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/MoiseevKW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/paap/MoradKW10,
author = {Tomer Y. Morad and
Avinoam Kolodny and
Uri C. Weiser},
title = {Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric
Chip Multiprocessors},
booktitle = {Third International Symposium on Parallel Architectures, Algorithms
and Programming, {PAAP} 2010, Dalian, China, 18-20 December, 2010},
pages = {65--72},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/PAAP.2010.50},
doi = {10.1109/PAAP.2010.50},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/paap/MoradKW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/GuzBKKMW09,
author = {Zvika Guz and
Evgeny Bolotin and
Idit Keidar and
Avinoam Kolodny and
Avi Mendelson and
Uri C. Weiser},
title = {Many-Core vs. Many-Thread Machines: Stay Away From the Valley},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {8},
number = {1},
pages = {25--28},
year = {2009},
url = {https://doi.org/10.1109/L-CA.2009.4},
doi = {10.1109/L-CA.2009.4},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/GuzBKKMW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DobkinGK09,
author = {Rostislav (Reuven) Dobkin and
Ran Ginosar and
Avinoam Kolodny},
title = {QNoC asynchronous router},
journal = {Integr.},
volume = {42},
number = {2},
pages = {103--115},
year = {2009},
url = {https://doi.org/10.1016/j.vlsi.2008.03.001},
doi = {10.1016/J.VLSI.2008.03.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DobkinGK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/MoiseevKW09,
author = {Konstantin Moiseev and
Avinoam Kolodny and
Shmuel Wimer},
title = {Power-delay optimization in {VLSI} microprocessors by wire spacing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {14},
number = {4},
pages = {55:1--55:28},
year = {2009},
url = {https://doi.org/10.1145/1562514.1562523},
doi = {10.1145/1562514.1562523},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/MoiseevKW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KolodnyP09,
author = {Avinoam Kolodny and
Li{-}Shiuan Peh},
title = {Special Section on International Symposium on Networks-on-Chip {(NOCS)}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {17},
number = {3},
pages = {317--318},
year = {2009},
url = {https://doi.org/10.1109/TVLSI.2009.2012524},
doi = {10.1109/TVLSI.2009.2012524},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KolodnyP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/VaisbandGKF09,
author = {Inna Vaisband and
Ran Ginosar and
Avinoam Kolodny and
Eby G. Friedman},
editor = {Fabrizio Lombardi and
Sanjukta Bhanja and
Yehia Massoud and
R. Iris Bahar},
title = {Power efficient tree-based crosslinks for skew reduction},
booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
Boston Area, MA, USA, May 10-12 2009},
pages = {285--290},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1531542.1531609},
doi = {10.1145/1531542.1531609},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/VaisbandGKF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/WalterCKS09,
author = {Isask'har Walter and
Israel Cidon and
Avinoam Kolodny and
Daniel Sigalov},
editor = {Maurizio Palesi and
Shashi Kumar},
title = {The era of many-modules SoC: revisiting the NoC mapping problem},
booktitle = {Second International Workshop on Network on Chip Architectures, NoCArc
2009, In conjunction with the 42nd Annual {IEEE/ACM} International
Symposium on Microarchitecture (MICRO-42), December 12, 2009, New
York, NY, {USA}},
pages = {43--48},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1645213.1645224},
doi = {10.1145/1645213.1645224},
timestamp = {Wed, 13 Feb 2019 11:42:26 +0100},
biburl = {https://dblp.org/rec/conf/micro/WalterCKS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/BerahaWCK09,
author = {Rudy Beraha and
Isask'har Walter and
Israel Cidon and
Avinoam Kolodny},
title = {The design of a latency constrained, power optimized NoC for a 4G
SoC},
booktitle = {Third International Symposium on Networks-on-Chips, {NOCS} 2009, May
10-13 2009, La Jolla, CA, {USA.} Proceedings},
pages = {86},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/NOCS.2009.5071449},
doi = {10.1109/NOCS.2009.5071449},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/BerahaWCK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/KrimerEKKW09,
author = {Evgeni Krimer and
Mattan Erez and
Isaac Keslassy and
Avinoam Kolodny and
Isask'har Walter},
title = {Packet-level static timing analysis for NoCs},
booktitle = {Third International Symposium on Networks-on-Chips, {NOCS} 2009, May
10-13 2009, La Jolla, CA, {USA.} Proceedings},
pages = {88},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/NOCS.2009.5071451},
doi = {10.1109/NOCS.2009.5071451},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/KrimerEKKW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/ManevichWCK09,
author = {Ran Manevich and
Isask'har Walter and
Israel Cidon and
Avinoam Kolodny},
title = {Best of both worlds: {A} bus enhanced NoC (BENoC)},
booktitle = {Third International Symposium on Networks-on-Chips, {NOCS} 2009, May
10-13 2009, La Jolla, CA, {USA.} Proceedings},
pages = {173--182},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/NOCS.2009.5071465},
doi = {10.1109/NOCS.2009.5071465},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/ManevichWCK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/WalterCK08,
author = {Isask'har Walter and
Israel Cidon and
Avinoam Kolodny},
title = {BENoC: {A} Bus-Enhanced Network on-Chip for a Power Efficient {CMP}},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {7},
number = {2},
pages = {61--64},
year = {2008},
url = {https://doi.org/10.1109/L-CA.2008.11},
doi = {10.1109/L-CA.2008.11},
timestamp = {Thu, 18 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/WalterCK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MoiseevWK08,
author = {Konstantin Moiseev and
Shmuel Wimer and
Avinoam Kolodny},
title = {On optimal ordering of signals in parallel wire bundles},
journal = {Integr.},
volume = {41},
number = {2},
pages = {253--268},
year = {2008},
url = {https://doi.org/10.1016/j.vlsi.2007.06.002},
doi = {10.1016/J.VLSI.2007.06.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MoiseevWK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/MoiseevKW08,
author = {Konstantin Moiseev and
Avinoam Kolodny and
Shmuel Wimer},
title = {Timing-aware power-optimal ordering of signals},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {13},
number = {4},
pages = {65:1--65:17},
year = {2008},
url = {https://doi.org/10.1145/1391962.1391973},
doi = {10.1145/1391962.1391973},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/MoiseevKW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PopovichSKF08,
author = {Mikhail Popovich and
Michael Sotman and
Avinoam Kolodny and
Eby G. Friedman},
title = {Effective Radii of On-Chip Decoupling Capacitors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {7},
pages = {894--907},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2000454},
doi = {10.1109/TVLSI.2008.2000454},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PopovichSKF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PopovichFSK08,
author = {Mikhail Popovich and
Eby G. Friedman and
Michael Sotman and
Avinoam Kolodny},
title = {On-Chip Power Distribution Grids With Multiple Supply Voltages for
High-Performance Integrated Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {7},
pages = {908--921},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2000515},
doi = {10.1109/TVLSI.2008.2000515},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PopovichFSK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MorgenshteinFGK08,
author = {Arkadiy Morgenshtein and
Eby G. Friedman and
Ran Ginosar and
Avinoam Kolodny},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Timing optimization in logic with interconnect},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {19--26},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353615},
doi = {10.1145/1353610.1353615},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MorgenshteinFGK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DobkinMKG08,
author = {Rostislav (Reuven) Dobkin and
Arkadiy Morgenshtein and
Avinoam Kolodny and
Ran Ginosar},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Parallel vs. serial on-chip communication},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {43--50},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353620},
doi = {10.1145/1353610.1353620},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DobkinMKG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/spaa/GuzKKW08,
author = {Zvika Guz and
Idit Keidar and
Avinoam Kolodny and
Uri C. Weiser},
editor = {Friedhelm Meyer auf der Heide and
Nir Shavit},
title = {Utilizing shared data in chip multiprocessors with the nahalal architecture},
booktitle = {{SPAA} 2008: Proceedings of the 20th Annual {ACM} Symposium on Parallelism
in Algorithms and Architectures, Munich, Germany, June 14-16, 2008},
pages = {1--10},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1378533.1378535},
doi = {10.1145/1378533.1378535},
timestamp = {Wed, 21 Nov 2018 11:14:43 +0100},
biburl = {https://dblp.org/rec/conf/spaa/GuzKKW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/GuzKKW07,
author = {Zvika Guz and
Idit Keidar and
Avinoam Kolodny and
Uri C. Weiser},
title = {Nahalal: Cache Organization for Chip Multiprocessors},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {6},
number = {1},
pages = {21--24},
year = {2007},
url = {https://doi.org/10.1109/L-CA.2007.6},
doi = {10.1109/L-CA.2007.6},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/GuzKKW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tocs/BeharMK07,
author = {Michael Behar and
Avi Mendelson and
Avinoam Kolodny},
title = {Trace cache sampling filter},
journal = {{ACM} Trans. Comput. Syst.},
volume = {25},
number = {1},
pages = {3},
year = {2007},
url = {https://doi.org/10.1145/1189736.1189739},
doi = {10.1145/1189736.1189739},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tocs/BeharMK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/GuzWBCGK07,
author = {Zvika Guz and
Isask'har Walter and
Evgeny Bolotin and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {Network Delays and Link Capacities in Application-Specific Wormhole
NoCs},
journal = {{VLSI} Design},
volume = {2007},
pages = {90941:1--90941:15},
year = {2007},
url = {https://doi.org/10.1155/2007/90941},
doi = {10.1155/2007/90941},
timestamp = {Thu, 16 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/GuzWBCGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/DobkinPLGK07,
author = {Rostislav (Reuven) Dobkin and
Yevgeny Perelman and
Tuvia Liran and
Ran Ginosar and
Avinoam Kolodny},
title = {High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link},
booktitle = {13th {IEEE} International Symposium on Asynchronous Circuits and Systems
{(ASYNC} 2007), 12-14 March 2006, Berkeley, California, {USA}},
pages = {3--14},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASYNC.2007.20},
doi = {10.1109/ASYNC.2007.20},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/DobkinPLGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BolotinCGK07,
author = {Evgeny Bolotin and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
editor = {Rudy Lauwereins and
Jan Madsen},
title = {Routing table minimization for irregular mesh NoCs},
booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition,
{DATE} 2007, Nice, France, April 16-20, 2007},
pages = {942--947},
publisher = {{EDA} Consortium, San Jose, CA, {USA}},
year = {2007},
url = {https://doi.org/10.1109/DATE.2007.364414},
doi = {10.1109/DATE.2007.364414},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BolotinCGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/BolotinGCGK07,
author = {Evgeny Bolotin and
Zvika Guz and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {The Power of Priority: NoC Based Distributed Cache Coherency},
booktitle = {First International Symposium on Networks-on-Chips, {NOCS} 2007, 7-9
May 2007, Princeton, New Jersey, USA, Proceedings},
pages = {117--126},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/NOCS.2007.42},
doi = {10.1109/NOCS.2007.42},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/BolotinGCGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/WalterCGK07,
author = {Isask'har Walter and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {Access Regulation to Hot-Modules in Wormhole NoCs},
booktitle = {First International Symposium on Networks-on-Chips, {NOCS} 2007, 7-9
May 2007, Princeton, New Jersey, USA, Proceedings},
pages = {137--148},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/NOCS.2007.8},
doi = {10.1109/NOCS.2007.8},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/WalterCGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Kolodny07,
author = {Avinoam Kolodny},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Networks on chips: keeping up with Rent's rule and Moore's law},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {55--56},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231968},
doi = {10.1145/1231956.1231968},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Kolodny07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/WimerMMK06,
author = {Shmuel Wimer and
Shay Michaely and
Konstantin Moiseev and
Avinoam Kolodny},
title = {Optimal bus sizing in migration of processor design},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {53-I},
number = {5},
pages = {1089--1100},
year = {2006},
url = {https://doi.org/10.1109/TCSI.2006.869902},
doi = {10.1109/TCSI.2006.869902},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/WimerMMK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MoreinisMWK06,
author = {Michael Moreinis and
Arkadiy Morgenshtein and
Israel A. Wagner and
Avinoam Kolodny},
title = {Logic Gates as Repeaters {(LGR)} for Area-Efficient Timing Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {14},
number = {11},
pages = {1276--1281},
year = {2006},
url = {https://doi.org/10.1109/TVLSI.2006.886400},
doi = {10.1109/TVLSI.2006.886400},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MoreinisMWK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/DobkinGK06,
author = {Rostislav (Reuven) Dobkin and
Ran Ginosar and
Avinoam Kolodny},
title = {Fast Asynchronous Shift Register for Bit-Serial Communication},
booktitle = {12th {IEEE} International Symposium on Asynchronous Circuits and Systems
{(ASYNC} 2006), 13-15 March 2006, Grenoble, France},
pages = {117--127},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ASYNC.2006.17},
doi = {10.1109/ASYNC.2006.17},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/DobkinGK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GuzWBCGK06,
author = {Zvika Guz and
Isask'har Walter and
Evgeny Bolotin and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
editor = {Georges G. E. Gielen},
title = {Efficient link capacity and QoS design for network-on-chip},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {9--14},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.243951},
doi = {10.1109/DATE.2006.243951},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GuzWBCGK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PopovichFSKS06,
author = {Mikhail Popovich and
Eby G. Friedman and
Michael Sotman and
Avinoam Kolodny and
Radu M. Secareanu},
editor = {Gang Qu and
Yehea I. Ismail and
Narayanan Vijaykrishnan and
Hai Zhou},
title = {Maximum effective distance of on-chip decoupling capacitors in power
distribution grids},
booktitle = {Proceedings of the 16th {ACM} Great Lakes Symposium on {VLSI} 2006,
Philadelphia, PA, USA, April 30 - May 1, 2006},
pages = {173--179},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1127908.1127951},
doi = {10.1145/1127908.1127951},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/PopovichFSKS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MoiseevWK06,
author = {Konstantin Moiseev and
Shmuel Wimer and
Avinoam Kolodny},
title = {Timing optimization of interconnect by simultaneous net-ordering,
wire sizing and spacing},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692589},
doi = {10.1109/ISCAS.2006.1692589},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MoiseevWK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SotmanKPF06,
author = {Michael Sotman and
Avinoam Kolodny and
Mikhail Popovich and
Eby G. Friedman},
title = {On-die decoupling capacitance: frequency domain analysis of activity
radius},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692629},
doi = {10.1109/ISCAS.2006.1692629},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SotmanKPF06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/DolevKK05,
author = {Noam Dolev and
Avner Kornfeld and
Avinoam Kolodny},
title = {Comparison of Sigma-delta Converter Circuit Architectures in Digital
Cmos Technology},
journal = {J. Circuits Syst. Comput.},
volume = {14},
number = {3},
pages = {515--532},
year = {2005},
url = {https://doi.org/10.1142/S0218126605002507},
doi = {10.1142/S0218126605002507},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/DolevKK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/BeharMK05,
author = {Michael Behar and
Avi Mendelson and
Avinoam Kolodny},
title = {Trace Cache Sampling Filter},
booktitle = {14th International Conference on Parallel Architectures and Compilation
Techniques {(PACT} 2005), 17-21 September 2005, St. Louis, MO, {USA}},
pages = {255--266},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/PACT.2005.38},
doi = {10.1109/PACT.2005.38},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/IEEEpact/BeharMK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PopovichFSK05,
author = {Mikhail Popovich and
Eby G. Friedman and
Michael Sotman and
Avinoam Kolodny},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {On-chip power distribution grids with multiple supply voltages for
high performance integrated circuits},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {2--7},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057665},
doi = {10.1145/1057661.1057665},
timestamp = {Wed, 15 Dec 2021 17:59:57 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PopovichFSK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MorgenshteinCGK05,
author = {Arkadiy Morgenshtein and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {Low-leakage repeaters for NoC interconnects},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {600--603},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464659},
doi = {10.1109/ISCAS.2005.1464659},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MorgenshteinCGK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BolotinCGK04,
author = {Evgeny Bolotin and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {Cost considerations in network on chip},
journal = {Integr.},
volume = {38},
number = {1},
pages = {19--42},
year = {2004},
url = {https://doi.org/10.1016/j.vlsi.2004.03.006},
doi = {10.1016/J.VLSI.2004.03.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BolotinCGK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/BolotinCGK04,
author = {Evgeny Bolotin and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {QNoC: QoS architecture and design process for network on chip},
journal = {J. Syst. Archit.},
volume = {50},
number = {2-3},
pages = {105--128},
year = {2004},
url = {https://doi.org/10.1016/j.sysarc.2003.07.004},
doi = {10.1016/J.SYSARC.2003.07.004},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/BolotinCGK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MoreinisMWK04,
author = {Michael Moreinis and
Arkadiy Morgenshtein and
Israel A. Wagner and
Avinoam Kolodny},
title = {Repeater insertion combined with {LGR} methodology for on-chip interconnect
timing optimization},
booktitle = {Proceedings of the 2004 11th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2004, Tel Aviv, Israel, December 13-15,
2004},
pages = {125--128},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ICECS.2004.1399630},
doi = {10.1109/ICECS.2004.1399630},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/MoreinisMWK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/BargerGK04,
author = {Anastasia Barger and
David Goren and
Avinoam Kolodny},
title = {Design and modelling of network on chip interconnects using transmission
lines},
booktitle = {Proceedings of the 2004 11th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2004, Tel Aviv, Israel, December 13-15,
2004},
pages = {403--406},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ICECS.2004.1399703},
doi = {10.1109/ICECS.2004.1399703},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/BargerGK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MichaelyWK04,
author = {Shay Michaely and
Shmuel Wimer and
Avinoam Kolodny},
title = {Optimal resizing of bus wires in layout migration},
booktitle = {Proceedings of the 2004 11th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2004, Tel Aviv, Israel, December 13-15,
2004},
pages = {411--414},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ICECS.2004.1399705},
doi = {10.1109/ICECS.2004.1399705},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/MichaelyWK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/BolotinMCGK04,
author = {Evgeny Bolotin and
Arkadiy Morgenshtein and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {Automatic hardware-efficient SoC integration by QoS network on chip},
booktitle = {Proceedings of the 2004 11th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2004, Tel Aviv, Israel, December 13-15,
2004},
pages = {479--482},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ICECS.2004.1399722},
doi = {10.1109/ICECS.2004.1399722},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/BolotinMCGK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MorgenshteinBCKG04,
author = {Arkadiy Morgenshtein and
Evgeny Bolotin and
Israel Cidon and
Avinoam Kolodny and
Ran Ginosar},
title = {Micro-modem - reliability solution for NoC communications},
booktitle = {Proceedings of the 2004 11th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2004, Tel Aviv, Israel, December 13-15,
2004},
pages = {483--486},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ICECS.2004.1399723},
doi = {10.1109/ICECS.2004.1399723},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/MorgenshteinBCKG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/issoc/MorgenshteinCKG04,
author = {Arkadiy Morgenshtein and
Israel Cidon and
Avinoam Kolodny and
Ran Ginosar},
title = {Comparative analysis of serial vs parallel links in NoC},
booktitle = {Proceedings of the 2004 International Symposium on System-on-Chip,
Tampere, Finland, November 16-18, 2004},
pages = {185--188},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ISSOC.2004.1411181},
doi = {10.1109/ISSOC.2004.1411181},
timestamp = {Mon, 09 Aug 2021 14:54:02 +0200},
biburl = {https://dblp.org/rec/conf/issoc/MorgenshteinCKG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MagenKWS04,
author = {Nir Magen and
Avinoam Kolodny and
Uri C. Weiser and
Nachum Shamir},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Interconnect-power dissipation in a microprocessor},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {7--13},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966750},
doi = {10.1145/966747.966750},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MagenKWS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ElboimKG03,
author = {Y. Elboim and
Avinoam Kolodny and
Ran Ginosar},
title = {A clock-tuning circuit for system-on-chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {616--626},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812371},
doi = {10.1109/TVLSI.2003.812371},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ElboimKG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MilterK03,
author = {O. Milter and
Avinoam Kolodny},
title = {Crosstalk noise reduction in synthesized digital logic circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1153--1158},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817551},
doi = {10.1109/TVLSI.2003.817551},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MilterK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MorgenshteinMWK03,
author = {Arkadiy Morgenshtein and
Michael Moreinis and
Israel A. Wagner and
Avinoam Kolodny},
editor = {Manfred Glesner and
Ricardo Augusto da Luz Reis and
Hans Eveking and
Vincent John Mooney III and
Leandro Soares Indrusiak and
Peter Zipf},
title = {Logic Gates as Repeaters {(LGR)} for Timing Optimization of SoC Interconnects},
booktitle = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,
1-3 December 2003},
pages = {99--104},
publisher = {Technische Universit{\"{a}}t Darmstadt, Insitute of Microelectronic
Systems},
year = {2003},
timestamp = {Thu, 07 Oct 2004 09:29:26 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MorgenshteinMWK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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