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2010 – 2019
- 2017
[c6]Jais Abraham, Uttam Garg, Glenn Colón-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, Martin Keim:
Adapting an industrial memory BIST solution for testing CAMs. ITC-Asia 2017: 112-117
1990 – 1999
- 1996
- [j2]Chennian Di, Jochen A. G. Jess:
An efficient CMOS bridging fault simulator: with SPICE accuracy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1071-1080 (1996) - 1994
- [c5]Hua Xue, Chennian Di, Jochen A. G. Jess:
Probability Analysis for CMOS Floating Gate Faults. EDAC-ETC-EUROASIC 1994: 443-448 - 1993
- [c4]Hua Xue, Chennian Di, Jochen A. G. Jess:
Fast Multi-Layer Critical Area Computation. DFT 1993: 117-124 - [c3]Hua Xue, Chennian Di, Jochen A. G. Jess:
A net-oriented method for realistic fault analysis. ICCAD 1993: 78-83 - [c2]Chennian Di, Jochen A. G. Jess:
On Accurate Modeling and Efficient Simulation of CMOS Opens. ITC 1993: 875-882 - [c1]Chennian Di, Jochen A. G. Jess:
On CMOS bridge fault modeling and test pattern evaluation. VTS 1993: 116-119 - 1992
- [j1]José Pineda de Gyvez, Chennian Di:
IC defect sensitivity for footprint-type spot defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5): 638-658 (1992)
Coauthor Index
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