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Luca Avallone
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2020 – today
- 2023
- [j5]Francesco Buccoleri
, Simone Mattia Dartizio
, Francesco Tesolin
, Luca Avallone
, Alessio Santiccioli
, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. IEEE J. Solid State Circuits 58(3): 634-646 (2023) - 2022
- [j4]Simone Mattia Dartizio
, Francesco Tesolin
, Mario Mercandelli
, Alessio Santiccioli
, Abanob Shehata
, Saleh Karman
, Luca Bertulessi
, Francesco Buccoleri
, Luca Avallone
, Angelo Parisi
, Andrea L. Lacaita
, Michael Peter Kennedy
, Carlo Samori
, Salvatore Levantino
:
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. IEEE J. Solid State Circuits 57(6): 1723-1735 (2022) - [j3]Simone Mattia Dartizio
, Francesco Buccoleri
, Francesco Tesolin
, Luca Avallone
, Alessio Santiccioli
, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. IEEE J. Solid State Circuits 57(12): 3538-3551 (2022) - [c4]Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
, Giovanni Steffan, Andrea Bevilacqua
, Luca Bertulessi
, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. CICC 2022: 1-2 - [c3]Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino:
A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. ISSCC 2022: 1-3 - 2021
- [j2]Luca Avallone
, Mario Mercandelli
, Alessio Santiccioli
, Michael Peter Kennedy
, Salvatore Levantino
, Carlo Samori
:
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2775-2786 (2021) - [c2]Mario Mercandelli
, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata
, Francesco Tesolin, Saleh Karman, Luca Bertulessi
, Francesco Buccoleri, Luca Avallone, Angelo Parisi
, Andrea Leonardo Lacaita
, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. ISSCC 2021: 445-447 - [c1]Alessio Santiccioli, Mario Mercandelli
, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata
, Luca Bertulessi
, Francesco Buccoleri, Luca Avallone, Angelo Parisi
, Dmytro Cherniak, Andrea L. Lacaita
, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. ISSCC 2021: 456-458 - 2020
- [j1]Luca Avallone
, Michael Peter Kennedy
, Saleh Karman
, Carlo Samori
, Salvatore Levantino
:
Jitter Minimization in Digital PLLs with Mid-Rise TDCs. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3): 743-752 (2020)
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