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Semantic ScholarIEEE Micro, Volume 15, 1995
Volume 15, Number 1, February 1995
- Paul L. Borrill, David E. Culler, Kathleen M. Nichols:
Guest Editors' Introduction: Hot Interconnects. 9-10 - Ronald Minnich, Dan Burns, Frank T. Hady:
The Memory-Integrated Network Interface. 11-20 - Matthias A. Blumrich, Cezary Dubnicki, Edward W. Felten, Kai Li, Malena R. Mesarina:
Virtual-Memory-Mapped Network Interfaces. 21-28 - Nanette J. Boden, Danny Cohen, Robert E. Felderman, Alan E. Kulawik, Charles L. Seitz, Jakov N. Seizovic, Wen-King Su:
Myrinet: A Gigabit-per-Second Local Area Network. 29-36 - Robert W. Horst:
TNet: A Reliable System Area Network. 37-45 - Thorsten von Eicken, Anindya Basu, Vineet Buch:
Low-Latency Communication Over ATM Networks Using Active Messages. 46-53 - Thomas E. Anderson, David E. Culler, David A. Patterson:
A Case for NOW (Networks Of Workstations). 54-64
- Yakov I. Fet:
Vertical Processing Systems: A Survey. 65-75
Volume 15, Number 2, April 1995
- Joe Circello, Greg Edgington, Dan McCarthy, James Gay, David Schimke, Steven Sullivan, Richard Duerden, Chris Hinds, Danny Marquette, Lal Sood, Al Crouch, Daniel Chow:
The superscalar architecture of the MC68060. 10-21 - Ruby B. Lee:
Accelerating multimedia with enhanced microprocessors. 22-32 - John H. Edmondson, Paul I. Rubinfeld, Ronald P. Preston, Vidya Rajagopalan:
Superscalar instruction execution in the 21164 Alpha microprocessor. 33-43 - Karl Wang, Christopher D. Bryant, Mike Carlson, T. Elmer, Adrian Harris, Michael J. Garcia, C. S. Hui, C. K. Leung, Brian K. Reynolds, Raymond Tang, Laura A. Weber, Jim Wenzel, Glen E. Wilson, Mike Becker:
Designing the MPC105 PCI bridge/memory controller. 44-49 - Janice M. Stone, Robert P. Fitzgerald:
Storage in the power PC. 50-58 - Roger D. Chamberlain, Robert R. Krchnavek:
Optically interconnected multicomputers using inverted-graph topologies. 59-69 - Bernd Klauer, Andreas Bleck, Klaus Waldschmidt:
The AM3 associative processor. 70-78 - Stephen L. Diamond:
Micro standards: IEEE std P1394. 81-83 - Dick Price:
Pentium FDIV flaw-lessons learned. 86-88
Volume 15, Number 3, June 1995
- Richard H. Stern:
Fuzziness versus all or nothing. 7 - Shane Greenstein:
The market and computer technology. 8-9 - Herbert Eichfeld, Martin Klimke, Manfred Menke, Jürgen Nolles, Thomas Künemund:
A general-purpose fuzzy inference processor. 12-17 - Richard Coggins, Marwan A. Jabri, Barry Flower, Stephen Pickard:
A low-power network for on-line diagnosis of heart patients. 18-25 - Andreas König, Peter Windirsch, Michael Gasteier, Manfred Glesner:
Visual inspection in industrial manufacturing. 26-31 - Eric Cosatto, Hans Peter Graf:
A neural network accelerator for image analysis. 32-38 - Marcello Chiaberge
, Leonardo Maria Reyneri:
Cintia: a neuro-fuzzy real-time controller for low-power embedded systems. 40-47 - Hans Peter Graf, Leonardo Maria Reyneri, D. C. Burns, I. Underwood, Alan F. Murray, D. G. Vass, Steven R. Skinner, James Edward Steck, Elizabeth C. Behrman, Lionel Tarassenko, Stefan Rüping, Karl Goser, Ulrich Rückert:
Neural networks-extraordinary variation. 48-59 - Ahmed Louri, James A. Hatch Jr., Jongwhoa Na:
A constant-time parallel sorting algorithm and its optical implementation. 60-71
Volume 15, Number 4, August 1995
- Richard H. Stern:
The PTO on software patents. 2-3 - Tsutomu Miki, Takeshi Yamakawa:
Fuzzy inference on an analog fuzzy chip. 8-18 - Witold Pedrycz, C. Hart Poskar, P. J. Czerowski:
A reconfigurable fuzzy neural network with in-situ learning. 19-30 - Donald L. Hung:
Dedicated digital fuzzy hardware. 31-39 - Hartmut Surmann, Ansgar Ungering:
Fuzzy rule-based systems on general-purpose processors. 40-48 - Fernando Vidal-Verdú, Ángel Rodríguez-Vázquez:
Using building blocks to design analog neuro-fuzzy controllers. 49-57 - Michael Milligan, Harvey G. Cragon:
Processor implementations using queues. 58-66 - Timothy J. Drabik, Albert H. Titus, Mark A. Handschy, David Banas, Stephen D. Gaalema, David J. Ward:
2D silicon/ferroelectric liquid crystal spatial light modulators. 67-76
Volume 15, Number 5, October 1995
- Vijay K. Madisetti, Thomas Egolf:
Virtual prototyping of embedded microcontroller-based DSP systems. 9-21 - Simon Segars, Keith Clarke, Liam Goudge:
Embedded control problems, Thumb, and the ARM7TDMI. 22-30 - Michael Dolle, Manfred Schlett:
A cost-effective RISC/DSP microprocessor for embedded systems. 32-40 - Gianluigi Castelli, Gianluca Ragazzini:
EOS: a real-time operating system adapts to application architectures. 41-49 - Manthos A. Tsoukarellas, Vassilis C. Gerogiannis, Kostis D. Economides:
Systematically testing a real-time operating system. 50-60 - Luis de Salvador, Julio Gutiérrez:
A multilevel systolic approach for fuzzy inference hardware. 61-71 - Michael Bekerman, Avi Mendelson:
A performance analysis of Pentium processor systems. 72-83
Volume 15, Number 6, December 1995
- Stephen L. Diamond:
Micro Web and uRAP. 2 - Shane Greenstein:
Not a Young and Restless Market. 3-4 - Tom Pittman:
The RISC penalty. 5 - Richard H. Stern:
Winsocking the competition. 6-7 - Atsushi Hasegawa, Ikuya Kawasaki, Kouji Yamada, Shinichi Yoshioka, Shumpei Kawasaki, Prasenjit Biswas:
SH3: high code density, low power. 11-19 - Kouhei Nadehara, Ichiro Kuroda, Masayuki Daito, Takashi Nakayama:
Low-power multimedia RISC. 20-29 - Masaki Kumanoya, Toshiyuki Ogawa, Kazunari Inoue:
Advances in DRAM interfaces. 30-36 - Makoto Awaga, Tatsushi Ohtsuka, Hideki Yoshizawa, Shigeru Sasaki:
3D graphics processor chip set. 37-45 - Hiroaki Takada, Ken Sakamura:
μITRON for small-scale embedded systems. 46-54 - Angel L. Enriquez, Adel H. Eltimsahy, Mohsin M. Jamali:
Flexible control for robot manipulators. 55-60 - Abraham Kandel, Giuseppe Ascia, Vincenzo Catania, Biagio Giacalone, Marco Russo, Lorenzo Vita, Andrés Jaramillo-Botero, Yoichi Miyake, Hua Harry Li, Nowell Godfrey, Yuandong Ji, Shuwei Guo, Liliane Peters, Krishna Rao Valavala, Mahmoud A. Manzoul, Antonio Ruiz, Julio Gutiérrez, Felipe Fernández:
Fuzzy Hardware Challenges. 61-67
- Giuseppe Ascia, Vincenzo Catania, Biagio Giacalone, Marco Russo, Lorenzo Vita:
Designing for parallel fuzzy computing. W1-W11 - Shuwei Guo, Liliane Peters:
A high-speed, reconfigurable fuzzy logic controller. W12-W22 - Andrés Jaramillo-Botero, Yoichi Miyake:
Parallel, high-speed PC fuzzy control. W23-W32 - Hua Harry Li, Nowell Godfrey, Yuandong Ji:
A Beam-and-Ball Controller Prototype. W33-W39 - Antonio Ruiz, Julio Gutiérrez, Felipe Fernández:
A fuzzy controller with an optimized defuzzification algorithm. W40-W49 - Krishna Rao Valavala, Mahmoud A. Manzoul:
A fuzzy partitioning system. W50-W57
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