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ORCIDMicroprocessors and Microsystems, Volume 60
Volume 60, July 2018
- Daniel Llamocca
, Daniel N. Aloi:
Self-reconfigurable implementation for a switched beam smart antenna. 1-14 - Golnaz Taheri, Ahmad Khonsari, Reza Entezari-Maleki, Mohammad Baharloo, Leonel Sousa:
Temperature-aware dynamic voltage and frequency scaling enabled MPSoC modeling using Stochastic Activity Networks. 15-23 - Claudio Copello, Ning Weng:
Adaptive scheduling to enhance data security and energy efficiency on energy harvesting platform. 24-37
- Jens Sparsø:
Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016. 38-39 - Sauvagya Ranjan Sahoo, Sudeendra Kumar K, Kamalakanta Mahapatra:
A novel configurable ring oscillator PUF with improved reliability using reduced supply voltage. 40-52 - Indar Sugiarto, Jörg Conradt:
Modular design of a factor-graph-based inference engine on a System-On-Chip (SoC). 53-64 - Debao Wei, Libao Deng, Mengqi Hao, Liyan Qiao, Xiyuan Peng:
A joint-LDPC decoding scheme based on retention error characteristics for MLC NAND flash memory. 65-76 - Muhammad Zeeshan, Syed Ali Jabir, Waqar Ahmed:
Joint algorithm for burst detection and AGC improvement in high throughput software defined radio waveform. 77-85 - Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, Lingkan Gong:
Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery. 86-95 - Ngoc-Hung Nguyen, Sheraz Ali Khan, Cheol-Hong Kim, Jong-Myon Kim:
A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms. 96-106 - Dinesh Kumar, Manoj Kumar:
Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs. 107-121 - Ebrahim Abiri, Abdolreza Darabi:
A novel modified GDI method-based clocked M/S-TFF for future generation microprocessor chips in nano schemes. 122-137 - Lang Li, Botao Liu, Yimeng Zhou, Yi Zou:
SFN: A new lightweight block cipher. 138-150 - Thorbjörn Posewsky, Daniel Ziener:
Throughput optimizations for FPGA-based deep neural network inference. 151-161 - Bi-ying Zhang, Zhongchuan Fu, Hongsong Chen, Gang Cui:
TCSTM: A task-characteristic-considered steady-state thermal model of multicore processors. 162-172
- Charles Effiong, Gilles Sassatelli, Abdoulaye Gamatié:
Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation. 173-184 - Rodrigo C. Surita, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo:
CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence. 185-195 - Jinwei Xu, Zhiqiang Liu, Jingfei Jiang, Yong Dou, Shijie Li:
CaFPGA: An automatic generation model for CNN accelerator. 196-206 - Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco:
Composition of switching lattices for regular and for decomposed functions. 207-218
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