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ORCIDIntegration, Volume 77
Volume 77, March 2021
- Jayachandran Remya
, P. C. Subramaniam, K. J. Dhanaraj:
A novel tunable gain CMOS buffer amplifier for large resistive loads. 1-12 - Jorge Alves Torres, João Costa Freire:
30 GHz SiGe active inductor with voltage controlled Q. 13-24 - Radhika V. Menon, Shantharam Kalipatnapu, Indrajit Chakrabarti:
High speed VLSI architecture for improved region based active contour segmentation technique. 25-37
- Han Zhou, Liang Chen, Sheldon X.-D. Tan:
Robust power grid network design considering EM aging effects for multi-segment wires. 38-47
- Seyed-Hosein Attarzadeh-Niaki, Ingo Sander, Mohammad Ahmadi:
An automated parallel simulation flow for cyber-physical system design. 48-58
- Sanjay Moulik:
RESET: A real-time scheduler for energy and temperature aware heterogeneous multi-core systems. 59-69
- Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das, Bhargab B. Bhattacharya:
Fast algorithms for test optimization of core based 3D SoC. 70-88 - Roohollah Sanati, Farzan Khatib, Mohammad Javadian Sarraf, Reihaneh Kardehi Moghaddam:
Low power time-domain rail-to-rail comparator with a new delay element for ADC applications. 89-95
- Haoyu Yang, Wei Zhong, Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu:
VLSI mask optimization: From shallow to deep learning. 96-103
- Dimitris Konstantinou, Chrysostomos Nicopoulos, Junghee Lee, Giorgos Dimitrakopoulos:
Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching. 104-112 - Engin Afacan, Nuno Lourenço, Ricardo Martins, Günhan Dündar:
Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test. 113-130 - Shuo Li, Junren Pan, Jin He, Zhiyuan Cao, Hao Wang, Sheng Chang, Qijun Huang:
A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links. 131-138 - Yuejun Zhang, Jiawei Wang, Pengjun Wang, Xiaoyong Xue, Xiaoyang Zeng:
Orthogonal obfuscation based key management for multiple IP protection. 139-150 - Gaurav Sharma, Lava Bhargava, Vinod Kumar:
Real-time automated register abstraction active power-aware electronic system level verification framework. 151-166 - Srinivas Katkoori, Sheikh Ariful Islam, Sujana Kakarla:
Partial evaluation based triple modular redundancy for single event upset mitigation. 167-179 - Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima:
Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing. 180-192 - Subhabrata Roy, Abhijit Chandra:
A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth. 193-204
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